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W99681CF JPEG USB DUAL MODE CAMERA CHIP
W99681CF JPEG USB Dual Mode Camera Chip
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Publication Release Date: March 2000 Revision A1
W99681CF
Revision History
Revision A1 Issue Date March, 2000 Formal release. Comments
Copyright by Winbond Electronics Corp., all rights reserved. The information in this document has been carefully checked and is believed to be correct as of the date of publication. Winbond Electronics Corp. reserves the right to make changes in the product or specification, or both, presented in this publication at any time without notice. Winbond assumes no responsibility or liability arising from the specification listed herein. Winbond makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patents, trademark, copyright, or rights of third parties. No license is granted by implication or other under any patent or patent rights of Winbond Electronics Corp. All other trademarks and registered trademarks are the property of their respective holders.
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W99681CF
TABLE OF CONTENTS
1 2 3 4 GENERAL DESCRIPTION.............................................................................................................. 7 FEATURES ....................................................................................................................................... 8 PIN CONFIGURATION .................................................................................................................. 10 PIN DESCRIPTION ........................................................................................................................ 11
4.1 PIN DEFINITION.................................................................................................................................. 11 4.2 PIN LIST............................................................................................................................................. 16 4.3 POWER-ON RESET INITIALIZATION ..................................................................................................... 17 5 6 7 SYSTEM DIAGRAM....................................................................................................................... 18 BLOCK DIAGRAM......................................................................................................................... 19 FUNCTIONAL DESCRIPTION...................................................................................................... 20
7.1 VIDEO INPUT INTERFACE.................................................................................................................... 20 7.1.1 Camera Control Serial Bus...................................................................................................... 20 7.1.2 Input Video Data Format.......................................................................................................... 20 7.1.3 Cropping.................................................................................................................................... 21 7.1.4 Scaling....................................................................................................................................... 21 7.1.5 Filtering...................................................................................................................................... 22 7.1.6 Captured Video Data Format................................................................................................... 22 7.2 DRAM CONTROL AND INTERFACE ..................................................................................................... 23 7.2.1 DRAM Access Arbitration ........................................................................................................ 23 7.2.2 DRAM Interface ........................................................................................................................ 23 7.3 JPEG COMPRESSION........................................................................................................................ 25 7.3.1 Level Shift and Forward DCT .................................................................................................. 25 7.3.2 Quantization.............................................................................................................................. 25 7.3.3 Huffman Encoding.................................................................................................................... 26 7.3.4 JPEG Encoding Order.............................................................................................................. 26 7.4 USB INTERFACE AND DEVICE CONTROL............................................................................................ 27 7.4.1 Endpoints..................................................................................................................................... 27
7.4.1.1 Default Endpoint (Endpoint 0)............................................................................................................27 7.4.1.2 Video Data-In Endpoint (Endpoint 1).................................................................................................27
7.4.2 USB Device Requests.............................................................................................................. 27
7.4.2.1 Standard Device Requests ................................................................................................................27 7.4.2.2 Video Camera Class-Specific Requests ...........................................................................................29 7.4.2.3 Vendor-Specific Requests .................................................................................................................29
7.4.3 Descriptors................................................................................................................................ 30
7.4.3.1 Device Descriptors .............................................................................................................................30 7.4.3.2 Configuration Descriptors ..................................................................................................................31 7.4.3.3 String Descriptors...............................................................................................................................33
7.5 VIDEO/STILL IMAGE DATA TRANSFER................................................................................................. 34 Publication Release Date: March 2000 Revision A1
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W99681CF
7.5.1 Output Video Data Format....................................................................................................... 34 7.5.2 Video Frame Synchronization ................................................................................................. 34 7.5.3 Bandwidth Management .......................................................................................................... 34 7.6 POWER MANAGEMENT....................................................................................................................... 35 7.6.1 W99681CF Reset..................................................................................................................... 35 7.6.2 Before Configured .................................................................................................................... 35 7.6.3 After Configured ....................................................................................................................... 35 7.6.4 Suspend .................................................................................................................................... 35 7.6.5 Resume..................................................................................................................................... 36 7.7 SERIAL EEPROM INTERFACE ........................................................................................................... 37 7.7.1 EEPROM Data Structure............................................................................................................ 37 7.7.2 EEPROM Operations ............................................................................................................... 37 7.8 MICROCONTROLLER INTERFACE ........................................................................................................ 39 7.8.1 Base Address Setup ................................................................................................................... 39 7.8.2 W99681CF Register Access ...................................................................................................... 39 7.8.3 Microcontroller Interrupt.............................................................................................................. 39 7.8.4 DRAM Access ............................................................................................................................. 39 7.8.5 IHV-Specific Information............................................................................................................. 40 8 CONTROL AND STATUS REGISTERS ...................................................................................... 41
8.1 GENERAL CONTROL REGISTERS........................................................................................................ 43 8.2 VIDEO INPUT CONTROL REGISTERS................................................................................................... 52 8.3 JPEG ENCODER CONTROL REGISTERS ............................................................................................ 63 9 ELECTRICAL CHARACTERISTICS ............................................................................................ 70
9.1 ABSOLUTE MAXIMUM RATINGS .......................................................................................................... 70 9.2 DC CHARACTERISTICS ...................................................................................................................... 70 9.2.1 USB Transceiver DC Characteristics...................................................................................... 70 9.2.2 Digital DC Characteristics........................................................................................................ 70 9.3 AC CHARACTERISTICS ...................................................................................................................... 71 9.3.1 USB Transceiver AC Characteristics...................................................................................... 71 9.3.2 RESET Timing AC Characteristics.......................................................................................... 72 9.3.3 Clock AC Characteristics ......................................................................................................... 73 9.3.4 Input Video AC Characteristics ............................................................................................... 73 9.3.5 DRAM Interface AC Characteristics........................................................................................ 74 9.3.6 EEPROM Interface AC Characteristics .................................................................................. 75 9.3.7 Microcontroller Interface AC Characteristics.......................................................................... 76 10 11 PACKAGE SPEC......................................................................................................................... 77 ORDERING INFORMATION ....................................................................................................... 78
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W99681CF
LIST OF FIGURES
FIGURE 3.1 W99681CF PIN CONFIGURATION ................................................................................................ 10 FIGURE 5.1 W99681CF-BASED USB DIGITAL VIDEO CAMERA SYSTEM DIAGRAM ......................................... 18 FIGURE 6.1 W99681CF BLOCK DIAGRAM ..................................................................................................... 19 FIGURE 7.1 INPUT VIDEO DATA FORMATS ..................................................................................................... 21 FIGURE 7.2 JPEG ENCODING ORDER............................................................................................................. 26 FIGURE 7.3 DEVICE CONFIGURATION ............................................................................................................ 27 FIGURE 7.4 EEPROM TIMING DIAGRAM....................................................................................................... 38 FIGURE 9.1 DATA SIGNAL RISE AND FALL TIME ............................................................................................ 71 FIGURE 9.2 DIFFERENTIAL DATA JITTER........................................................................................................ 71 FIGURE 9.3 DIFFERENTIAL TO EOP TRANSITION SKEW AND EOP WIDTH ....................................................... 71 FIGURE 9.4 RECEIVER JITTER TOLERANCE..................................................................................................... 72 FIGURE 9.5 RESET TIMING .......................................................................................................................... 72 FIGURE 9.6 CLOCK WAVEFORM .................................................................................................................... 73 FIGURE 9.7 INPUT VIDEO TIMING .................................................................................................................. 73 FIGURE 9.8 DRAM INTERFACE INPUT TIMING ............................................................................................... 74 FIGURE 9.9 DRAM INTERFACE OUTPUT TIMING............................................................................................ 74 FIGURE 9.10 EEPROM INTERFACE TIMING ................................................................................................... 75 FIGURE 9.11 MICROCONTROLLER INTERFACE TIMING.................................................................................... 76 FIGURE 10.1 128L QFP (14X20X2.75MM FOOTPRINT 3.2MM) DIMENSIONS ....................................................... 77
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LIST OF TABLES
TABLE 4.1 W99681CF PIN LIST ................................................................................................................. 16 TABLE 4.2 POWER-ON RESET CONFIGURATION DEFINITIONS ...................................................................... 17 TABLE 7.1 CAPTURED VIDEO DATA FORMAT ............................................................................................... 22 TABLE 7.2 SDRAM AND EDO DRAM INTERFACE SIGNALS........................................................................ 23 TABLE 7.3 STANDARD DEVICE REQUESTS ................................................................................................... 28 TABLE 7.4 W99681CF VENDOR-SPECIFIC REQUESTS ............................................................................... 29 TABLE 7.5 W99681CF DEVICE DESCRIPTOR.............................................................................................. 30 TABLE 7.6 W99681CF CONFIGURATION DESCRIPTOR ............................................................................... 31 TABLE 7.7 W99681CF VIDEO INTERFACE DESCRIPTOR ............................................................................. 31 TABLE 7.8 W99681CF DATA-IN ENDPOINT DESCRIPTOR ........................................................................... 32 TABLE 7.9 W99681CF VIDEO INTERFACE ALTERNATE SETTING 1-16 INTERFACE DESCRIPTOR ................. 32 TABLE 7.10 W99681CF ALTERNATE SETTING 1-16 DATA-IN ENDPOINT DESCRIPTOR............................... 33 TABLE 7.11 THE MAXIMUM DATA PAYLOAD SIZE IN BYTES FOR ALTERNATE SETTINGS............................... 33 TABLE 7.12 W99681CF DEFAULT STREAM DESCRIPTORS ......................................................................... 33 TABLE 7.13 OUTPUT VIDEO DATA FORMAT ................................................................................................. 34 TABLE 7.14 EEPROM DATA STRUCTURE ..................................................................................................... 37 TABLE 8.1 W99681CF CONTROL REGISTER MAP ......................................................................................... 41 TABLE 9.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 70 TABLE 9.2 USB TRANSCEIVER DC CHARACTERISTICS .................................................................................. 70 TABLE 9.3 DIGITAL DC CHARACTERISTICS..................................................................................................... 70 TABLE 9.4 USB TRANSCEIVER AC CHARACTERISTICS................................................................................... 72 TABLE 9.5 RESET TIMING............................................................................................................................. 73 TABLE 9.6 CLOCK AC CHARACTERISTICS ...................................................................................................... 73 TABLE 9.7 INPUT VIDEO AC CHARACTERISTICS ............................................................................................. 74 TABLE 9.8 DRAM INTERFACE AC CHARACTERISTICS.................................................................................... 74 TABLE 9.9 EEPROM INTERFACE AC CHARACTERISTICS .............................................................................. 75 TABLE 9.10 MICROCONTROLLER INTERFACE AC CHARACTERISTICS.............................................................. 76
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W99681CF
1
GENERAL DESCRIPTION
The W99681CF is a digital video processing chip offered by Winbond to facilitate adapterless connection between digital video camera and personal computer for video and still image capturing and editing, video e-mail, and video conferencing applications. Low-cost, high-performance, and highquality digital video camera can be realized by using Winbonds W99681CF, which includes Universal Serial Bus (USB) technology and the international standard JPEG compression. The digital video camera is becoming the next great input device for the PC. USB is now a common PC standard for connecting peripheral products, which features low cost, hot-attachable plug and play, adequate 12 Mb/s full speed bandwidth, and simultaneous attachment of multiple devices. The W99681CF has built-in full speed USB controller which benefits from using the isochronous data transfer mode of the USB bus, and which is compliant with the full power management requirements of the USB specification, including startup, operating, and suspend modes. To prevent saturation of the USB bus, the W99681CF uses no more than 8 Mb/s of available bandwidth to ensure the continued operation of other low bandwidth devices such as USB mice and keyboards. Although USB provides a low-cost solution for low to medium speed peripherals, its 12 Mb/s bandwidth is not enough for high-quality and high-performance digital video camera. High-quality and low-cost compression is necessary to boost frame rate for a high-performance digital video camera. The W99681CF has built-in the baseline JPEG compression, which corresponds to the ISO/IEC international standard 10918-1, with YCbCr4:2:2 or YCbCr4:2:0 components in non-interleaved scan. The baseline JPEG implementation in the W99681CF includes Discrete Cosine Transform (DCT), quantization, zig-zag scan, and Huffman encoder. With JPEG compression, the W99681CF can easily achieve good quality 30 frames per second (fps) in CIF resolution (352x288) and 10~15 fps in VGA resolution (640x480) by consuming no more than 8 Mb/s USB bandwidth. The W99681CF can accept NTSC, PAL, or VGA video in 8- or 16-bit YCbCr4:2:2 format, square or rectangular pixels, and converts to sub-QCIF (128x96), QCIF (176x144), CIF (128x96), SIF (352x240), 320x240, or VGA (640x480) format. Built-in cropping window control and arbitrary scaling in both the horizontal and vertical directions can serve as the digital pan and zoom over a user-specified region for camera control. In addition to USB interface, the W99681CF also supports an 8-bit microcontroller interface for portable PC camera applications. Up to 24 still images in 640x480 VGA format can be captured, JPEG compressed, and stored into an external 2 Mbytes Flash memory when in the portable mode. An on-chip DRAM controller is used to interface to SDRAM or EDO DRAM through a 16-bit data bus. An external serial E2PROM is also supported if IHV-specific Vendor ID and Product ID are needed. The IHV-specific information can be also provided by an external microcontroller if present to save the cost of an E2PROM. The W99681CF is a 3.3 V device with TTL-compatible 3.3 V or 5.0 V I/O, and is packaged in a 128L QFP.
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2
FEATURES
q USB Interface
* * * * * * * * *
Fully compliant with USB Specification Revision 1.1 Supports for full speed devices with maximum 12 Mb/s USB bandwidth Uses no more than 8 Mb/s USB bandwidth to prevent saturation of the USB bus Provides multiple alternate settings for various isochronous bandwidth consumptions Does not use isochronous bandwidth for default alternate setting 0 Complies with USB power management requirements USB Control and Isochronous transfers On-chip USB full speed transceivers Bus-powered high power devices
q Video Compression
* * * * * *
Fully compliant with ISO/IEC 10918-1 international JPEG standard On-chip DCT, quantization, zig-zag scan, and Huffman encoder Contains two AC and two DC Huffman code tables, and two programmable quantization tables Supports baseline sequential mode in YCbCr4:2:2 or YCbCr4:2:0 non-interleaved scan Encodes in sub-QCIF (128x96), QCIF (176x144), CIF (352x288), SIF (352x240), 320x240, or VGA (640x480) picture format Encodes sub-QCIF/QCIF/CIF/SIF/320x240 format at 30 frames per second (fps), VGA format at 10~15 fps
q Video Pre-processing
* * * *
Direct connect to digital camera through an 8- or 16-bit data bus Glueless interface to NTSC/PAL TV decoder Input video format compliant with YCbCr 4:2:2 CCIR 601 standard Built-in cropping, arbitrary scaling, and filtering functions for digital pan and zoom camera control
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W99681CF
q Video Output
* * *
Video output can be either compressed bit stream or original video Compressed bit stream is fully compliant with ISO baseline JPEG standard in YCbCr4:2:2 or YCbCr4:2:0 non-interleaved scan Original video output can be in YCbCr4:2:2 or YCbCr4:2:0 packed format
q DRAM Interface
* * *
Supports SDRAM or 1-cycle EDO DRAM Supports SDRAM Self Refresh Supports 16-bit DRAM interface in 0.5, 1, 2 or 4 Mbytes configuration
q Serial EEPROM Interface
*
Supports optional 1K (128x8) serial EEPROM for IHV-specific Vendor ID and Product ID
q Supports Hardware and Software Snap Shot q Supports 8-bit Microcontroller Interface for Portable PC Camera Applications q Built-in PLL (Phase-Locked Loops) Clock Synthesizer q Operating Frequency is 48 MHz with Video Input Frequency of 13.5 MHz (typical) q 3.3 V Device with TTL-compatible 3.3 V or 5.0 V I/O q 128L QFP Package
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3
PIN CONFIGURATION
The W99681CF is packaged in a 128L QFP. The pin configuration is shown in Figure 3.1.
Figure 3.1 W99681CF Pin Configuration
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ALE VDDI CLK24M AD0 AD1 AD2 AD3 VSSP AD4 AD5 AD6 AD7 VDDP A8/GPIO0 A9/GPIO1 A10/GPIO2 A11/GPIO3 A12/GPIO4 A13/GPIO5 A14/GPIO6 A15/GPIO7
VDDP UV0 UV1 UV2 UV3 UV4 UV5 UV6 UV7 VSSP XIN XOUT VDDP INT# RD# WR#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
MD2 MD13 MD1 MD14 VDDP VDDI MD0 MD15 VSSP SDE#/SDS SCLK SDATA VS HS Y0 Y1 Y2 Y3 VSSI Y4 Y5 Y6 Y7 VSSP VICLK VDD5V
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
CAS0#/DQM0 VDDP CAS1#/DQM1 MD7 MD8 MD6 MD9 VSSP MD5 MD10 MD4 MD11 MD3 MD12
W99681CF
(Top View)
RAS0#/CS0# RAS1#/CS1# SRAS# VSSI OE#/CKE SCAS# SMCLK VSSP WE#
MA3 MA4 MA2 MA5 VSSP MA1 VDDP MA6 MA0 MA7 MA10 MA8 MA9 BA VSSP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 VSSP SDA/EEPROM SCL VDDP VDDI VPO VMO TOE# RSTOUT RCV VP VM USBVDD DP DM USBVSS SUSPND PWRDWN PWRDWN# RSTIN# INTXTR AVSS AVDD VSSI TEST# EXTMCU
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
W99681CF
4
PIN DESCRIPTION
The following signal types are used in these descriptions. I IU B O AIO P G # Input pin Input pin with internal pull-up resistor Bi-directional input/output pin Output pin Analog input/output pin Power supply pin Ground pin Active low
4.1 Pin Definition
USB and External Transceiver Interface (8 pins) Pin Name DM DP Pin Number 50 51 Type AIO AIO Description Data Minus line of differential USB upstream port. Data Plus line of differential USB upstream port. Note: provide an external 1.5 K pull-up resistor at DP so the device indicates to the host that it is a full-speed device. VM VP RCV TOE# VMO VPO 53 54 55 57 58 59 IU IU IU O O O Single-ended Receiver Input of the data minus line. Single-ended Receiver Input of the data plus line. Differential Receiver Input. Output Enable for external transceiver. Data Minus Output to the differential driver. Data Plus Output to the differential driver.
DRAM Interface (37 pins) Pin Name MD[15:0] MA[10:0] Pin Number 92-95, 97-106, 109-110 65-68, 70, 7277 Type B O Description Data Bus. Address Bus. Note: for SDRAM, MA[10:0] are sampled during the ACTIVE
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command (row address MA[10:0]) and READ/WRITE command (column address MA[7:0], with MA10 defining AUTO PRECHARGE) to select one location out of the 521K available in the respective bank. MA10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (MA10 HIGH). BA 78 O EDO DRAM: Not used. SDRAM: Bank Address Input. BA defines to which internal bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. BA is also used to program the 12th bit of the Mode Register. RAS[1:0]# CS[1:0]# CAS[1:0]# DQM[1:0] 89, 90 O 80, 81 O EDO DRAM: Row Address Strobes. SDRAM: Chip Select. CS# enables the command decoder for the SDRAM. EDO DRAM: Column Address Strobes. SDRAM: Input/Output Mask. DQM[1:0] are input mask signals for write accesses and output enable signals for read accesses. DQM0 corresponds to MD[7:0]; DQM1 corresponds to MD[15:8]. 84 O EDO DRAM: Output Enable. SDRAM: Clock Enable. CKE activates the SMCLK signal. The SDRAM enters precharge power-down to deactivate the input and output buffers, excluding CKE, for maximum power saving when CKE is LOW coincident with a NOP. 88 O EDO DRAM: Write Enable. SDRAM: Command Input. SRAS#, SCAS#, and WE# (along with CS#) define the command being entered. SRAS# 82 O EDO DRAM: Not used. SDRAM: Command Input. SRAS#, SCAS#, and WE# (along with CS#) define the command being entered. SCAS# 85 O EDO DRAM: Not used. SDRAM: Command Input. SRAS#, SCAS#, and WE# (along with CS#) define the command being entered. SMCLK 86 O EDO DRAM: Not used. SDRAM: Clock.
OE# CKE
WE#
Input Video Interface (22 pins) Pin Name Y[7:0] Pin Number 117-120, 122125 Type I Description Digital Y (Luminance) Inputs in 16-bit Mode, or Digital YUV Inputs in 8-bit Mode.
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W99681CF
UV[7:0] HS VS VICLK SDE#/SDS SCLK SDATA 2-9 116 115 127 112 113 114 I I I I O B B Digital UV (Chrominance) Inputs in 16-bit Mode, or Not Used in 8-bit Mode. Horizontal Sync Input. Programmable polarity. Vertical Sync Input. Programmable polarity. Input Video Clock. Serial Data Enable/Serial Data Strobe. Serial Interface Clock. Serial Interface Data.
Micro Controller Interface (21 pins) Pin Name AD[7:0] A[15:8] GPIO[7:0] ALE RD# WR# CS# SANP# INT# 14 O 18 15 16 17 Pin Number 21-24, 26-29 31-38 Type B I B I IU IU IU Description Multiplexed Address/Data Bus. EXTMCU = 1: High-order Address Bus. EXTMCU = 0: General Purpose I/Os. Address Latch Enable. ALE is used to enable the address latch that separates the address from the data on AD bus. Data Read Strobe. Data Write Strobe. EXTMCU = 1: Chip Select. EXTMCU = 0: Snap Shot Input. Interrupt Output, level-triggered.
Serial E2PROM Interface (2 pins) Pin Name SCL SDA/EEPRO M Pin Number 62 63 Type O B Description Serial Clock. Serial Data/Serial E2PROM Detection. During a reset operation, the W99681CF samples this signal to see if an external E2PROM exists. A 10K ohm pull-up resistor should be used if an external E2PROM is used; otherwise it should be tied to VSS.
Miscellaneous (11 pins) Pin Name Pin Number Type Description
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W99681CF
XIN 11 I Reference frequency input from a crystal or a clock source. It should be 48 Mhz if PLL is off (PLLSEL = 0) or 12 Mhz if PLL is on (PLLSEL = 1) for full-speed device. Oscillator output to a crystal. This pin is left unconnected if an external clock source is employed. 24 Mhz Clock Output. External Micro Controller (MCU). 0: no; 1: yes. Test Input. Internal USB Transceiver Select. 0: off; 1: on. System Reset Input. Low-active Power Down Control. This pin is active upon reset, suspended, or when the Camera Power-on Control register (CR00_4) is 0. Once active, it remains active until the CR00_4 is set to 1. High-active Power Down Control. This pin is active upon reset, suspended, or when the Camera Power-on Control register (CR00_4) is 0. Once active, it remains active until the CR00_4 is set to 1. USB Suspend Mode. This pin is active when the W99681CF is in the suspend mode. It is cleared to 0 when the W99681CF is resumed, or reset by RSTIN# pin or a USB reset command. Reset Output. This pin is active when RSTIN# pin is active, or a USB reset command is received.
XOUT CLK24M EXTMCU TEST# INTXTR RSTIN# PWRDWN#
12 20 39 40 44 45 46
O O I IU I IU O
PWRDWN
47
O
SUSPND
48
O
RSTOUT
56
O
Power and Ground (27 pins) Pin Name VDD5V VDDP VSSP Pin Number 128 1, 13, 30, 61, 71, 91, 107 10, 25, 64, 69, 79, 87, 96, 111, 126 52 49 42 43 19, 60, 108 Type P P G Description 5V Buffer Power Supply. Provide 5V power to the I/O buffers for 5V input tolerance. +4.4 V ~ +5.25 V. Buffer Power Supply. Provide isolated power to the I/O buffers for improved noise immunity. +3.3 V 0.3 V. Buffer Ground.
USBVDD USBVSS AVDD AVSS VDDI
P G P G P
USB Transceiver Power Supply. +3.3 V 0.3 V. USB Transceiver Ground. PLL Power Supply. +3.3 V 0.3 V. PLL Ground. Core Logic Power Supply. +3.3 V 0.3 V.
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W99681CF
VSSI 41, 83, 121 G Core Logic Ground.
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4.2 Pin List
Table 4.1 W99681CF Pin List Pin Name Pin Name Pin Name Pin 1 VDDP 33 A10/GPIO2 65 MA3 97 2 UV0 34 A11/GPIO3 66 MA4 98 3 UV1 35 A12/GPIO4 67 MA2 99 4 UV2 36 A13/GPIO5 68 MA5 100 5 UV3 37 A14/GPIO6 69 VSSP 101 6 UV4 38 A15/GPIO7 70 MA1 102 7 UV5 39 EXTMCU 71 VDDP 103 8 UV6 40 TEST# 72 MA6 104 9 UV7 41 VSSI 73 MA0 105 10 VSSP 42 AVDD 74 MA7 106 11 XIN 43 AVSS 75 MA10 107 12 XOUT 44 INTXTR 76 MA8 108 13 VDDP 45 RSTIN# 77 MA9 109 14 INT# 46 PWRDWN# 78 BA 110 15 RD# 47 PWRDWN 79 VSSP 111 16 WR# 48 SUSPND 80 RAS0#/CS0# 112 17 CS#/SNAP# 49 USBVSS 81 RAS1#/CS1# 113 18 ALE 50 DM 82 SRAS# 114 19 VDDI 51 DP 83 VSSI 115 20 CLK24M 52 USBVDD 84 OE#/CKE 116 21 AD0 53 VM 85 SCAS# 117 22 AD1 54 VP 86 SMCLK 118 23 AD2 55 RCV 87 VSSP 119 24 AD3 56 RSTOUT 88 WE# 120 25 VSSP 57 TOE# 89 CAS0#/DQM0 121 26 AD4 58 VMO 90 CAS1#/DQM1 122 27 AD5 59 VPO 91 VDDP 123 28 AD6 60 VDDI 92 MD7 124 29 AD7 61 VDDP 93 MD8 125 30 VDDP 62 SCL 94 MD6 126 31 A8/GPIO0 63 SDA/EEPROM 95 MD9 127 32 A9/GPIO1 64 VSSP 96 VSSP 128 Note 1. All output and bi-directional pins, except XOUT pin, are tri-stated during reset. Name MD5 MD10 MD4 MD11 MD3 MD12 MD2 MD13 MD1 MD14 VDDP VDDI MD0 MD15 VSSP SDE#/SDS SCLK SDATA VS HS Y0 Y1 Y2 Y3 VSSI Y4 Y5 Y6 Y7 VSSP VICLK VDD5V
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W99681CF
4.3 Power-on Reset Initialization
During power-on reset, states of the memory data lines MD[7:0] are latched into the W99681CFs internal configuration registers as device configuration information. Since each pin of MD[7:0] is internally pulled up on its I/O buffer, no external pull-up resistor is required. For pull-down, a 4.7K ohm resistor is recommended. Table 4.2 describes the power-on reset configuration definitions. Table 4.2 Power-on Reset Configuration Definitions MD Bit MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Definition Normal operation Force suspend mode if suspend mode is enabled Suspend mode is disabled Suspend mode is enabled Isochronous handshake phase is enabled Isochronous handshake phase is disabled Internal RCV comes from SIE Internal RCV comes from USB Transceiver PLL Disable PLL Enable Low Power, Bus-powered Devices High Power, Bus-powered Devices EDO DRAM SDRAM 256Kx DRAM 1Mx DRAM CR00_8 CR00_9 CR00_10 CR00_11 CR00_12 CR00_13 CR00_14 Conf Reg CR00_15
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5
SYSTEM DIAGRAM
Video Memory 1Mx16 SDRAM
CCD/CMOS Sensor
Video
Sensor DSP
YCbCr 4:2:2
W99681CF
JPEG or original 8-bit uC
USB
optional
Serial E2 PROM 128x8
optional
Figure 5.1 W99681CF-Based USB Digital Video Camera System Diagram
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W99681CF
6
BLOCK DIAGRAM
Video Memory
W99681CF
DRAM Controller
Quantization
Zig-zag
Video In
YCbCr 4:2:2
VPRE
DCT
VLE
XIN PLL XOUT Device Controller USB SIE
USB XCVRs
D+ D-
8-bit uC Serial E2PROM
Figure 6.1 W99681CF Block Diagram
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7
7.1
FUNCTIONAL DESCRIPTION
Video Input Interface
Video input data is cropped, down-scaled, and filtered in the video pre-processing (VPRE) block, then is stored into the DRAM as captured video for the following JPEG compression and transfer. 7.1.1 Camera Control Serial Bus A dedicated programmable serial bus is supported for camera control. The serial bus includes SCLK, SDATA, and SDE#/SDS signals. During serial bus read, these signals are controlled by the host via bits 4-0 of the Serial Bus Control register (CR01_4-0). There are two serial bus write modes which are controlled by bit 5 of the Serial Bus Control register (CR01_5).: normal serial bus write mode (CR01_5 = 0) and fast serial bus write mode (CR01_5 = 1). Normal serial bus write mode (CR01_5 = 0): SDATA and SCLK signals are output from CR01_1-0 directly. Fast serial bus write mode (CR01_5 = 1): SDATA and SCLK signals are output from CR06-CR09 in about 400 Khz bit frequency. 7.1.2 Input Video Data Format The W99681CF accepts video data in YUV 4:2:2 format through a 16-bit (Y[7:0] and UV[7:0]) or 8-bit (Y[7:0]) data bus. Many YUV ordering formats are supported which are selected by bits 9-8 of the Video Capture Control register (CR26) as shown in Figure 7.1. Video data can be latched by the W99681CF by using either rising-edge or falling-edge of the VICLK clock signal. In the 8-bit modes the VICLK frequency is twice the pixel rate, only Y[7:0] pins are used for video data input and UV[7:0] pins are not used.
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W99681CF
VICLK Y[7:0] UV[7:0] Y[7:0] UV[7:0] Y[7:0] Y[7:0] Y[7:0]
Y0 U0 Y1 V0 Y2 U2 Y3 V2 Y4 U4 Y5 V4 Y6 U6
16-bit UV Mode (CR26_10-8=00x)
Y0 V0 Y1 U0 Y2 V2 Y3 U2 Y4 V4 Y5 U4 Y6 V6
16-bit VU Mode (CR26_10-8=01x)
Y0 U0 Y1 V0 Y2 U2 Y3
8-bit YUYV Mode (CR26_10-8=100)
U0 Y0 V0 Y1 U2 Y2 V2
8-bit UYVY Mode (CR26_10-8=101)
Y0 V0 Y1 U0 Y2 V2 Y3
8-bit YVYU Mode (CR26_10-8=110) Y[7:0]
V0 Y0 U0 Y1 V2 Y2 U2
8-bit VYUY Mode (CR26_10-8=111)
Figure 7.1 Input Video Data Formats 7.1.3 Cropping A cropping rectangle (or window) is supported for cropping or clipping the incoming video data. Only interested video data located inside the cropping rectangle is processed and sent to the host system. The cropping rectangle can be moved within the input rectangle by programming the Cropping Window Start X and Cropping Window Start Y registers. Cropping is performed based on the VS signal for vertical cropping and HS signal for horizontal cropping. Both VS and HS are programmable polarity for maximum flexibility. 7.1.4 Scaling The cropped video can be down-scaled horizontally and/or vertically. The horizontal down-scaling and vertical down-scaling are performed independently by using two DDAs (Digital Differential Accumulator) with Captured Video Width Horizontal Down - scaling Factor = and Cropping Window End X - Cropping Window Start X Captured Video Height Vertical Down - scaling Factor = . Cropping Window End Y - Cropping Window Start Y The W99681CF does not perform up-scaling during video pre-processing. To produce CIF format from 240-line video for the JPEG compression, a special vertical up-scaling can be performed by the JPEG Publication Release Date: March 2000 Revision A1
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encoder. For the original video transfer, the CIF format from 240-line video can be produced by the software driver. 7.1.5 Filtering A 3-tap or 5-tap FIR filter is used to reduce noise and aliasing artifacts produced by the CCD or CMOS sensor, and the scaling process. 7.1.6 Captured Video Data Format After cropped, down-scaled, and filtered in the video pre-processing (VPRE) block, the input video is stored into the DRAM as captured video. Four different formats are supported for the captured video: YUV4:2:2 packed, YUV4:2:0 packed, YUV4:2:2 planar, and YUV4:2:0 planar modes, which are selected by bits 1-0 of the Video Capture Control register (CR26) as described in Table 7.1. YUV4:2:2 and YUV4:2:0 packed modes are used for original video transfer, while YUV4:2:2 and YUV4:2:0 planar modes are used for JPEG compression video transfer. Table 7.1 Captured Video Data Format CR26_1-0 00 01 10 11 Captured Video Data Format YUV4:2:2 packed mode for original video transfer YUV4:2:0 packed mode for original video transfer YUV4:2:2 planar mode for JPEG compression video transfer YUV4:2:0 planar mode for JPEG compression video transfer
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W99681CF
7.2 DRAM Control and Interface
The W99681CF supports 256Kx16 and 1Mx16 SDRAM or EDO DRAM in a 0.5 ~ 4 Mbytes configuration with 16-bit data bus. A single 1Mx16, -15 or above, SDRAM is recommended for better cost/performance. 7.2.1 DRAM Access Arbitration The DRAM arbiter helps to maximize performance by orchestrating memory access requests from internal engines. Two priority levels are defined for these requests: * First priority: DRAM refresh request and SDRAM mode register write request * Second priority: Capture FIFO write request, DCT read request, VLE read request, VLE FIFO write request, USB FIFO read request, and USB control read/write request Programmable FIFO status are provided by the Capture FIFO, VLE FIFO, and USB FIFO such that the DRAM Controller arbitrates according to these FIFO status to prevent any video data loss and to achieve the best performance. 7.2.2 DRAM Interface The DRAM controller provides many programmable controls for the DRAM operations which include: * DRAM Type: supports SDRAM and EDO DRAM * DRAM Address: programmable 9-bit (256Kx EDO DRAM), 10-bit (1Mx EDO DRAM or 256Kx SDRAM), and 12-bit (1Mx SDRAM) address * DRAM Timing: adjustable Trp, Trcd, Tras, and Tcas timings * DRAM Refresh: 1 ~ 8 refresh cycles per scan line * SDRAM Read Latency: 1 ~ 3 clocks * SDRAM Burst Type: sequential or interleaved * SDRAM Burst Length: 1, 2, 4, 8, or full page * SDRAM Self Refresh Table 7.2 shows the interface signals for SDRAM and EDO DRAM. Table 7.2 SDRAM and EDO DRAM Interface Signals Pin Name MD[15:0] MA[10:0] BA RAS[1:0]#/CS[1:0]# RAS[1:0]# RAS[1:0]# 256Kx EDO DRAM MD[15:0] MA[8:0] 1Mx EDO DRAM MD[15:0] MA[9:0] 256Kx SDRAM MD[15:0] MA[8:0] BA CS[1:0]# 1Mx SDRAM MD[15:0] MA[10:0] BA CS[1:0]#
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CAS[1:0]#/DQM[1:0] OE#/CKE WE# SRAS# SCAS# SMCLK CAS[1:0]# OE# WE# CAS[1:0]# OE# WE# DQM[1:0] CKE WE# SRAS# SCAS# SMCLK DQM[1:0] CKE WE# SRAS# SCAS# SMCLK
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W99681CF
7.3 JPEG Compression
The W99681CF supports JPEG baseline sequential process for video data compression. For the sequential DCT-based mode, 8x8 sample blocks are typically input block by block from left to right, and block-row by block-row from top to bottom. Each block is transformed by the forward DCT (FDCT) into a set of 64 values referred to as DCT coefficients. Each of the 64 coefficients is then quantized using one of 64 corresponding values from a quantization table. After quantization, the DC coefficients and the 63 AC coefficients are converted into a one-dimensional zig-zag sequence, then are passed to a Huffman encoder for entropy encoding procedure which compresses the data further. 7.3.1 Level Shift and Forward DCT Prior to computing the FDCT the input data are level shifted to a signed twos complement representation. For 8-bit precision the level shift is achieved by subtracting 128. The following equation specifies the mathematical definition of the FDCT.
Svu =
where
7 7 (2x + 1)u (2 y + 1)v 1 CuCv syx cos cos 4 16 16 x = 0 y =0
Cu, Cv = 1
for u, v = 0 2 Cu, Cv = 1 otherwise
7.3.2 Quantization After the FDCT is computed for a block, each of the 64 resulting DCT coefficients is quantized by a uniform quantizer. The uniform quantizer is defined by the following equation. Rounding is to the nearest integer:
Svu Sqvu = round Qvu
The quantizer step size for each coefficient Svu is the value of the corresponding element Qvu from the quantization table. The W99681CF supports two programmable quantization tables, luminance quantization table and chrominance quantization table, which are made by two internal 64x8 SRAMs, and which should be loaded by the host via the USB bus before start of the JPEG compression. The quantized DCT coefficient values are signed, twos complement integers with 11-bit precision for 8-bit input precision.
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7.3.3 Huffman Encoding After quantization, the quantized coefficients are converted to the zig-zag sequence for Huffman encoding. The DC coefficients are coded differently from the AC coefficients. The value that should be encoded is the difference (DIFF) between the quantized DC coefficient of the current block (DCi which is also designated as Sq00) and that of the previous block of the same component (PRED):
DIFF = DCi - PRED
At the beginning of the scan and at the beginning of each restart interval, the prediction for the DC coefficient prediction is initialized to 0. For the AC coefficient encoding, since many AC coefficients are zero, runs of zeros are identified and coded efficiently. In addition, if the remaining coefficients in the zig-zag sequence order are all zero, this is coded explicitly as an end-of-block (EOB). The W99681CF Huffman encoder employs two DC and two AC Huffman tables within one scan for luminance and chrominance components. 7.3.4 JPEG Encoding Order The W99681CF JPEG encoder supports two non-interleaved encoding orders shown in Figure 7.2: * YUV4:2:2 non-interleaved encoding order * YUV4:2:0 non-interleaved encoding order
Y1
Y2
Y3
Y4
U1
U2
U3
V1
V2
V3
Y1, Y2, ...Yn Scan 1
U1, U 2, ...Un/2 V1, V2, ...Vn/2 Scan 2 Scan 3
YUV4:2:2 Non-interleaved Encoding Order
Yn
Un/2
Vn/2
Y1 Y3
Y2 Y4
Y1, Y2, ...Yn Scan 1
U1 U2 V1 V2
U1, U 2, ...Un/4 V1, V2, ...Vn/4 Scan 2 Scan 3
YUV4:2:0 Non-interleaved Encoding Order
Yn
Un/4
Vn/4
Figure 7.2 JPEG Encoding Order
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W99681CF
7.4 USB Interface and Device Control
The W99681CF contains two endpoints: default and Video Data-In endpoints. Figure 7.3 shows the device configuration for the W99681CF-based USB digital video camera.
W9967CF-Based
Default Pipe
Host
Data-In Pipe
Device
Figure 7.3 Device Configuration 7.4.1 Endpoints 7.4.1.1 Default Endpoint (Endpoint 0) The default endpoint uses control transfers as defined in the USB specification. The default endpoint provides access to the W99681CF-based devices configuration, status, and control information by sending standard, class, and vendor-specific requests to the device, an interface, or an endpoint. 7.4.1.2 Video Data-In Endpoint (Endpoint 1) The Video Data-In endpoint is used to receive video image data from the device intended for delivery to a video capture application on the host. The Video Data-In endpoint uses isochronous transfers. The direction is always IN. The maximum packet size can be varied for different alternate settings for limited USB bandwidth. 7.4.2 USB Device Requests The W99681CF responds to requests from the host on the default pipe. The W99681CF supports standard, class, and vendor-specific USB device requests. 7.4.2.1 Standard Device Requests The W99681CF supports the standard USB device requests as shown in Table 7.3 and described below. It responds to standard device requests whether it has been assigned a non-default address or is currently configured. If any unrecognized or unsupported standard request is received, it returns STALL.
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Table 7.3 Standard Device Requests bmRequestType 00000010B bRequest CLEAR_FEATURE (1) wValue Feature Selector (0) 10000000B 10000000B GET_CONFIGURATION (8) GET_DESCRIPTOR (6) Zero Descriptor Type and Descriptor Index Zero Zero Zero Zero or Language ID Interface (0) Zero Interface Endpoint SET_ADDRESS (5) SET_CONFIGURATION (9) Device Address Configura -tion Value Zero Zero Zero Zero One Descriptor Length Configuration Value Descriptor wIndex Endpoint wLength Zero Data None
10000001B 10000000B 10000001B 10000010B 00000000B 00000000B
GET_INTERFACE (10) GET_STATUS (0)
One Two
Alternate Setting Device, Interface, or Endpoint Status None None
00000000B 00000010B
SET_DESCRIPTOR (7) (Not Supported) SET_FEATURE (3) Feature Selector (0) Alternate Setting Endpoint Zero None
00000001B 00000010B
SET_INTERFACE (11) SYNCH_FRAME (12) (Not Supported)
Interface (0)
Zero
None
Clear Feature
The W99681CF supports the following Clear Feature request: * When directed to an endpoint recipient for ENDPOINT_STALL
The W99681CF returns STALL if any unrecognized or unsupported Clear Feature request is received. Get Configuration The W99681CF returns zero if it is unconfigured or the bConfiguration value defined in the Configuration Descriptor is configured. Get Descriptor The W99681CF supports Get Descriptor requests for standard descriptors (Device, Configuration, and String). The W99681CF returns STALL if a Get Descriptor request is received for a class-specific descriptor or a vendor-specific descriptor, is unrecognized or unsupported. - 28 -
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Get Interface The W99681CF supports a Get Interface request for Interface 0 by returning the selected alternate setting. The default alternate setting is zero. The W99681CF returns STALL for a Get Interface request for any other Interface or any Get Interface request before the Device is configured. Get Status The W99681CF supports a Get Status directed at the device, Interface 0, or any defined endpoint (default or Video Data-In). The W99681CF returns STALL if a Get Status request is received for Interface 0 or any defined endpoint before the Device is configured, or if a Get Status request is received for any unrecognized or unsupported recipient. Set Address The W99681CF supports a Set Address request to change the Device Address from the default address (zero) to a unique address. Set Configuration The W99681CF supports Set Configuration requests to set the Device Configuration to zero (unconfigured) or the bConfiguration value defined in the Configuration Descriptor. The W99681CF returns STALL if a Set Configuration request is received with any other value. Set Descriptor The W99681CF does not support update for any defined Descriptor (Device, Configuration, Interface, Endpoint, or String). It returns STALL for any Set Descriptor request. Clear Feature The W99681CF supports the following Set Feature request: * When directed to an endpoint recipient for ENDPOINT_STALL The W99681CF returns STALL if any unrecognized or unsupported Set Feature request is received. Set Interface When configured, the W99681CF supports a Set Interface request to Interface 0 for defined Alternate Settings. This request allows the host to select the desired alternate setting. The W99681CF returns STALL for any other Set Interface request. Synch Frame The W99681CF returns STALL for any Synch Frame request.
7.4.2.2 Video Camera Class-Specific Requests Currently, there is no class-specific request is defined for the video camera devices. The W99681CF returns STALL for any class-specific request. 7.4.2.3 Vendor-Specific Requests The W99681CF supports two vendor-specific requests for the control registers In/Out transfers on the default pipe (Endpoint 0): Get W99681CF Control and Set W99681CF Control. The vendor-specific requests defined for the W99681CF are shown in Table 7.4. The W99681CF returns STALL if an unrecognized or unsupported vendor-specific request is received. Table 7.4 W99681CF Vendor-Specific Requests bmRequestType 11000000B bRequest GET_W99681CF_CONTROL (1) wValue Zero wIndex Index
1
wLength Length
2
Data Data
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01000000B SET_W99681CF_CONTROL (0) Data03 Index1 Length2 Data
Note 1. Index specifies the starting index of the control registers to be accessed. An index counter, loaded with the Index value, will be incremented by one after every two bytes of data transferred. Note 2. Length specifies number of data bytes transferred during the second phase of the control transfer. It should be an even number value. If this field is zero, there is no data transfer phase. Note 3. Data0 is a word-sized data to be programmed into the control register indexed by the Index field, no matter the Length field is zero or not. The internal index counter will be incremented by one once Data0 is transferred. Get W99681CF Control The W99681CF supports a Get W99681CF Control request for W99681CF control registers IN transfer. Length field should be an even number value. The W99681CF returns STALL for any unrecognized or unsupported Get W99681CF Control request. Set W99681CF Control The W99681CF supports a Set W99681CF Control request for W99681CF control registers OUT transfer. Length field should be an even number value. If the Length field is zero, only Data0 is transferred with no data transfer phase. The W99681CF returns STALL for any unrecognized or unsupported Set W99681CF Control request. 7.4.3 Descriptors The W99681CF supports the standard USB descriptors as described below. The W99681CF returns STALL if a request is received for any unrecognized or unsupported standard descriptor. 7.4.3.1 Device Descriptors The W99681CF returns a Device Descriptor with the values shown in Table 7.5. Table 7.5 W99681CF Device Descriptor Offset 0 1 2 4 5 6 7 8 10 12 14 15 Field bLength bDescriptorType bcdUSB bDeviceClass bDeviceSubClass bDeviceProtocol bMaxPacketSize0 idVendor idProduct bcdDevice iManufacturer iProduct Size 1 1 2 1 1 1 1 2 2 2 1 1 Value 0x12 0x01 0x0110 0x00 0x00 0x00 0x08 0x1046 0x9967 0x0110 0x01 0x02 - 30 Description Size of this descriptor in bytes Device Descriptor Type USB Specification Release Number in BCD Class code Subclass code Protocol code Maximum packet size for endpoint zero Vendor ID Product ID Device release number in BCD Index of string descriptor describing manufacturer Index of string descriptor describing product
W99681CF
16 17 iSerialNumber bNumConfigurations 1 1 0x00 0x01 Index of string descriptor describing the devices serial number Number of possible configurations
Note 1. Vendor ID and Product ID will be replaced with bytes 0-3 of an external serial E2PROM or uC if present. 7.4.3.2 Configuration Descriptors The W99681CF returns a Configuration Descriptor and other configuration related descriptors as described below. When the host requests the Configuration Descriptor, all related interface and endpoint descriptors are returned. Table 7.6 W99681CF Configuration Descriptor Offset 0 1 2 Field bLength bDescriptorType wTotalLength Size 1 1 2 Value 0x09 0x02 0x0119 Description Size of this descriptor in bytes Configuration Descriptor Type Total length of data returned for this configuration. Includes the combined length of all descriptors returned for this configuration. Number of interfaces supported by this configuration Value used as an argument to Set Configuration to select this configuration No configuration string Configuration characteristics Maximum power consumption from the bus when the device is fully operational. Expressed in 2 mA units.
4 5 6 7 8
bNumberInterfaces bConfigurationValue iConfiguration bmAttributes Maxpower
1 1 1 1 1
0x01 0x01 0x00 0x80 0xFA or 0x32 (Note 1)
Note 1. Value of this field is 0xFA (500 mA) for high power devices (CR00_10 = 1), or 0x32 (100 mA) for low power devices (CR00_10 = 0). Table 7.7 W99681CF Video Interface Descriptor Offset 0 1 2 3 4 5 Field bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass Size 1 1 1 1 1 1 Value 0x09 0x04 0x00 0x00 0x01 0x00 Description Size of this descriptor in bytes Interface Descriptor Type Number of interface Default alternate setting zero Number of endpoints used by this interface Image interface class code
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6 7 8 bInterfaceSubClass bInterfaceProtocol iInterface 1 1 1 0x00 0x00 0x00 Digital Video Camera subclass code Protocol code. No class specific protocol. No interface string
Table 7.8 W99681CF Data-In Endpoint Descriptor Offset 0 1 2 3 4 6 Field bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize bInterval Size 1 1 1 1 2 1 Value 0x07 0x05 0x81 0x01 0x00 0x01 Description Size of this descriptor in bytes Endpoint Descriptor Type Endpoint number. Direction is set to IN. Isochronous transfer type Default zero bandwidth Interval in milliseconds for polling endpoint for data transfers
The W99681CF Video interface includes 16 alternate settings that allow the Data-In endpoint bandwidth to be varied decreasingly from 8 Mbps down to 0.5 Mbps in descending 0.5 Mbps steps such that the device driver can request subsequently smaller bandwidth quantities. A separate interface descriptor and its associated endpoint are included for each setting. When the host requests the Configuration Descriptor, all 16 pairs of interface and endpoint descriptors for alternate setting should follow the interface and endpoint descriptors for the default alternate setting zero. The W99681CF supports the Get Interface and Set Interface requests to report or select a specific alternate setting for the Video interface. Table 7.9 W99681CF Video Interface Alternate Setting 1-16 Interface Descriptor Offset 0 1 2 3 4 5 6 7 8 Field bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iInterface Size 1 1 1 1 1 1 1 1 1 Value 0x09 0x04 0x00 1-16 (Note 1) 0x01 0x00 0x00 0x00 0x00 Description Size of this descriptor in bytes Interface Descriptor Type Number of interface Alternate setting 1-16 for this interface Number of endpoints used by this interface Image interface class code Digital Video Camera subclass code Protocol code. No class specific protocol. No interface string
Note 1. Refer to Table 7.11.
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Table 7.10 W99681CF Alternate Setting 1-16 Data-In Endpoint Descriptor Offset 0 1 2 3 4 6 Field bLength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize bInterval Size 1 1 1 1 2 1 Value 0x07 0x05 0x81 0x01 Note 1 0x01 Description Size of this descriptor in bytes Endpoint Descriptor Type Endpoint number. Direction is set to IN. Isochronous transfer type Maximum packet size of this alternate setting Interval in milliseconds for polling endpoint for data transfers
Note 1. Refer to Table 7.11. Table 7.11 shows bAlternateSetting fields and wMaxPacketSize fields for these alternate settings. Table 7.11 The Maximum Data Payload Size in Bytes for Alternate Settings Alternate Setting bAlternateSetting wMaxPacketSize 1 1 2 2 3 3 895 4 4 831 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16
1023 959
767 703 639 575 511 447 383 319 255 191 127 63
7.4.3.3 String Descriptors The W99681CF includes strings describing the manufacturer and product as shown in Table 7.12. Table 7.12 W99681CF Default Stream Descriptors Offset 0 1 2 4 5 6 20 21 22 Field bLength bDescriptorType bString bLength bDescriptorType bString bLength bDescriptorType bString Size 1 1 2 1 1 14 1 1 14 Value 0x04 0x03 0x0409 0x10 0x03 Description Length of String descriptor in bytes String Descriptor Type Array of two-byte LangID codes (English American) Length of String descriptor in bytes String Descriptor Type
WINBOND Manufacturer 0x10 0x03 W99681C F Length of String descriptor in bytes String Descriptor Type Product
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7.5 Video/Still Image Data Transfer
Video or still image data from the device is delivered to the host system through an isochronous pipe (Endpoint 1). The maximum packet size can be varied for different alternate settings for limited USB bandwidth for other USB devices. 7.5.1 Output Video Data Format The W99681CF supports two video transfer modes: original video transfer mode and JPEG compression video transfer mode. The captured video stored in the DRAM will be compressed by the JPEG encoder and then transferred to the host if JPEG compression video transfer mode is selected, or will be directly transferred to the host if original video transfer mode is selected. Four different formats are supported for the output video which are selected by bits 1-0 of the Video Capture Control register (CR26) and bits 1 of the JPEG Encoder Control register (CR39) as described in Table 7.13. Table 7.13 Output Video Data Format CR39_1 0 0 1 1 1 CR26_1-0 00 01 0X 10 11 Output Video Data Format Original YUV4:2:2 packed mode Original YUV4:2:0 packed mode Reserved JPEG YUV4:2:2 non-interleaved scan mode JPEG YUV4:2:0 non-interleaved scan mode
7.5.2 Video Frame Synchronization A single video frame typically requires multiple USB packets. One or more zero length isochronous data packets are used to mark the end of a video frame. The first non-zero data packet is the start of the next video frame. If an error is encountered during the reception of a USB packet, the host may discard the entire video frame. Processing begins again with the next video frame as indicated by the first non-zero length isochronous data packet after one or more zero-length packet. 7.5.3 Bandwidth Management The W99681CF provides for varying the bandwidth required by providing a zero-bandwidth interface (alternate setting zero) and 16 alternate settings interfaces with 8 Mbps down to 0.5 Mbps bandwidth in descending 0.5 Mbps steps. The default alternate setting zero (with zero bandwidth) selected by a Set Configuration request allows a video camera to be initially configured even on a highly utilized USB bus. Before the device begins streaming video data, the host software must select an alternate setting with the appropriate amount of bandwidth by using the Set Interface request.
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7.6 Power Management
The W99681CF provides three output pins as described below for the video camera power management to meet the USB specification requirements. * PWRDWN/PWRDWN#: These pins, when active, are used to turn off the USB 5V power supply to the video source circuits (CCD/CMOS sensor device, ADC, DSP, video decoder, etc.). * SUSPND: This pin, when active, is used to turn off the 3.3V power supply to the W99681CF (excluding USBVDD pin, the power supply for the transceiver), DRAM, and E2PROM. Bit 10 of the Miscellaneous Control register (CR00) determines whether the W99681CF-based device is a high power device or a low power device as described below: * CR00_10 = 1: High power, bus-powered devices. They must draw no more than 100 mA upon power up and may draw up to 500 mA after being configured. * CR00_10 = 0: Low power, bus-powered devices. May draw up to 100 mA from their upstream connection to allow the interface to function when the remainder of the hub is powered down. 7.6.1 W99681CF Reset The W99681CF has two reset sources: system reset from the input RSTIN# pin, and the USB reset detected by seeing a single-ended zero (SE0) for more than 2.5 us. All reset sources are joined inside the W99681CF into a single reset signal which initializes the W99681CF and is also output via the RSTOUT pin to initialize other external circuits. Reset can wake the W99681CF from the suspended mode (SUSPND is inactive low) and turn off the USB 5V power supply to the video source circuits (PWRDWN is active high and PWRDWN# is active low). 7.6.2 Before Configured Before configured, the W99681CF should be reset and keep PWRDWN and PWRDWN# to be active (CR00_4 = 0) such that the W99681CF-based devices will not draw more than 100 mA from the USB bus power supply. It is required that an external power-on reset should be applied to the RSTIN# pin before any USB transaction is sent to the W99681CF by the host. 7.6.3 After Configured After configured, PWRDWN and PWRDWN# pins should be inactive by programming the Camera Power-on Control register to one (CR00_4 = 1) to enable device functions. The W99681CF-based devices must draw less than 100 mA (CR00_10 = 0) or 500 mA (CR00_10 = 1) from the bus during normal operation. The SOF (Start of Frame) packet is guaranteed to occur once a frame to keep full speed devices awake during normal bus operation. 7.6.4 Suspend The W99681CF goes into the suspend mode from any powered state when it sees a constant idle state Publication Release Date: March 2000 Revision A1
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on the USB bus lines for more than 3.0 ms. When suspended, both SUSPND and PWRDWN are active high, PWRDWN# is active low, and the Camera Power-on Control register is cleared to zero (CR00_4 = 0). The W99681CF-based devices must draw less than 500 uA from the bus when suspended. 7.6.5 Resume Once the W99681CF is in the suspended state, it can be resumed by receiving non-idle signaling on the bus. SUSPND will be inactive low when resumed. PWRDWN and PWRDWN# will remain active until the Camera Power-on Control register is set to one (CR00_4 = 1) by the host.
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7.7
Serial EEPROM Interface
The W99681CF supports an external 1K (128x8) serial E2PROM as an optional source for IHV-specific Vendor ID and Product ID. The external E2PROM data, in stead of the default data, will be used when a high is sampled at SDA pin (pin 49) during a reset operation. 7.7.1 EEPROM Data Structure The E2PROM contains IHV-specific Vendor ID and Product ID as described in Table 7.14. Table 7.14 EEPROM Data Structure Address Field 0x00 0x02 0x04 idVendor idProduct Size 2 2 2 Value TL Description Total length of E2PROM data to be returned Vendor ID Product ID
7.7.2 EEPROM Operations The external E2PROM will be only read right after a reset operation. TL (defined in address 0x00) bytes of data will be read by using a sequential read operation. START condition: A high-to-low transition of SDA with SCL high is a start condition which must proceed any other command. STOP condition: A low-to-high transition of SDA with SCL high is a stop condition which terminates all communications. After a read sequence, the stop command will place the E2PROM in a standby power mode. ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the E2PROM in 8-bit words. The E2PROM will acknowledge by pulling SDA low after receiving each address. The W99681CF will likewise acknowledge by pulling SDA low after receiving each data word. This must happen during the ninth clock cycle after each word received and after all other devices have freed the SDA bus. Refer to Figure 7.4, a sequential read is initiated by the W99681CF with a start condition followed by a 7-bit data word address (always 0) and a high read bit. The E2PROM will respond with an acknowledge and then serially output 8 data bits. After the W99681CF receives an 8-bit data word, it responds with an acknowledge. As long as the E2PROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. The sequential read operation is terminated when the memory address limit (TL) is reached and the W99681CF does not respond with an acknowledge but does generate a following stop condition.
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SDA SCL
START STOP 8 9
SCL SDA IN SDA OUT
START
START ACK R/W
1
ACKNOWLEDGE
ACK ACK DATA 0 DATA 1 DATA 127
STOP NO ACK
WORD ADDRESS (0)
SDA
MSB LSB
Sequential Read
Figure 7.4 EEPROM Timing Diagram
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W99681CF
7.8 Microcontroller Interface
The W99681CF supports an external 8-bit microcontroller to access DRAM and W99681CF internal registers for portable PC camera applications. 7.8.1 Base Address Setup The W99681CF internal registers occupy 256-byte microcontroller address space. A special base address (BA) setup mechanism, described as followed, is designed for the microcontroller to configure base address for the W99681CF internal register access: 1 assert hardware reset. 2 write the key, ! ! W 9 9 6 7 ! in ASCII code, to the port xx00H. 3 the port address, xx00H, then will be used as Base Address (BA) for the microcontroller access. The setup procedure must be executed right after the hardware reset. Once the procedure is finished, the xx00H address will be used as the base address until another hardware reset is asserted. 7.8.2 W99681CF Register Access Since all internal registers are 16-bit wide, it takes two cycles for the microcontroller to access one 16bit register through the 8-bit data bus. The two microcontroller access cycles should be in low-byte then high-byte order. For example, to write CR00 register, the microcontroller must write to BA + 00H address at first, then write to BA + 01H address to complete this 16-bit register access. 7.8.3 Microcontroller Interrupt The W99681CF interrupts the microcontroller by forcing INT# pin to low when it completes a still image capture (original video mode) or JPEG compression of this image (JPEG compression mode). Once interrupt is acknowledged by the microcontroller, it must write one to bit 5 of the Miscellaneous Control register (CR00_5) to clear the interrupt. Interrupt can also be disabled by writing zero to bit 6 of the Miscellaneous Control register (CR00_6). 7.8.4 DRAM Access The external microcontroller can read/write access DRAM through W99681CF by using the following registers: uC Access DRAM Start Address Register (BA + 18H ~ 1AH): specifies the 21-bit starting WORD address of the DRAM to be accessed. uC Access DRAM Mode Select (bit 8 of BA + 1BH): specifies read or write access mode. uC Access DRAM Data Port Register (BA + 1CH ~ 1DH): 16-bit data port which stores data read from DRAM in read mode, or data to be written into DRAM in write mode. Read Access (uC reads data from DRAM)
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1 DRAM Start Address Setup. Program the 21-bit WORD address to BA + 18H (bits 7-0), BA + 19H (bits 15-8), then BA + 1AH (bits 20-16). 2 Read Access Mode Setup. Program 0 to bit 0 of BA + 1BH to select read mode. W99681CF then starts accessing 16-bit DRAM data into the internal latches, and the internal DRAM address will be increased by 1 automatically after the access. 3 Read Low-Byte DRAM Data. Read low-byte DRAM data from BA + 1CH location. 4 Read High-Byte DRAM Data. Read high-byte DRAM data from BA + 1DH location. The W99681CF starts accessing the next-address DRAM data and the internal DRAM address will be increased by 1 automatically after the access. 5 Read Contiguous DRAM Data. Repeat steps 3 and 4 for contiguous DRAM data accesses. Write Access (uC writes data to DRAM) 1 DRAM Start Address Setup. Program the 21-bit WORD address to BA + 18H (bits 7-0), BA + 19H (bits 15-8), then BA + 1AH (bits 20-16). 2 Write Access Mode Setup. Program 1 to bit 0 of BA + 1BH to select write mode. 3 Write Low-Byte DRAM Data. Write low-byte DRAM data into BA + 1CH location. 4 Write High-Byte DRAM Data. Write high-byte DRAM data into BA + 1DH location. The W99681CF then starts writing the 16-bit data into DRAM and the internal DRAM address will be increased by 1 automatically after the access. 5 Write Contiguous DRAM Data. Repeat steps 3 and 4 for contiguous DRAM data accesses. 7.8.5 IHV-Specific Information The microcontroller can provide IHV-specific information including Vendor ID, Product ID, Device release number, and string descriptors of manufacturer, product, and devices serial number as that of E2PROM to save the cost of an E2PROM. Maximum 128 bytes information can be provided and data structure is the same as that of E2PROM shown in Table 7.14. All IHV-specific information must be written to the W99681CF via the Vendor String Data Port register (CR0F) in word-aligned sequence right after hardware reset and base address is set up.
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8
CONTROL AND STATUS REGISTERS
The internal W99681CF control registers can be accessed by performing one of the two vendor-specific requests on the default pipe (Endpoint 0): Get W99681CF Control for read access and Set W99681CF Control for write access. All W99681CF control registers are 16-bit wide and can be accessed in WORD only. Table 8.1 shows the control register map. Table 8.1 W99681CF Control Register Map Index 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0020H 0021H uC Address BA + 00H - 01H BA + 02H - 03H BA + 04H - 05H BA + 06H - 07H BA + 08H - 09H BA + 0AH - 0BH BA + 0CH - 0DH BA + 0EH - 0FH BA + 10H - 11H BA + 12H - 13H BA + 18H - 19H BA + 1AH - 1BH BA + 1CH - 1DH BA + 1EH - 1FH BA + 20H - 21H BA + 22H - 23H BA + 24H - 25H BA + 26H - 27H BA + 28H - 29H BA + 2AH - 2BH BA + 2CH - 2DH BA + 2EH - 2FH BA + 30H - 31H BA + 40H - 41H BA + 42H - 43H Symbol CR00 CR01 CR02 CR03 CR04 CR05 CR06 CR07 CR08 CR09 CR0C CR0D CR0E CR0F CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR20 CR21 Description Miscellaneous Control Register Serial Bus Control Register General I/O Port Control Register DRAM Timing Control Register SDRAM Control Register Memory Controller Test Mode Control Register Fast Serial Bus Write Register 0 Fast Serial Bus Write Register 1 Fast Serial Bus Write Register 2 Fast Serial Bus Write Register 3 uC Access DRAM Start Address Low Register uC Access DRAM Start Address High Register uC Access DRAM Data Port Register Vendor String Register Cropping Window Start X Register Cropping Window Start Y Register Cropping Window End X Register Cropping Window End Y Register Captured Video Width Register Captured Video Height Register Video Capture Control Register Video Capture Test Mode Control Register Capture Test Data Register Capture Y Frame Buffer 0 Start Address Low Register Capture Y Frame Buffer 0 Start Address High Register
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0022H 0023H 0024H 0025H 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 0040H-5FH 0060H-7FH BA + 44H - 45H BA + 46H - 47H BA + 48H - 49H BA + 4AH - 4BH BA + 4CH - 4DH BA + 4EH - 4FH BA + 50H - 51H BA + 52H - 53H BA + 54H - 55H BA + 56H - 57H BA + 58H - 59H BA + 5AH - 5BH BA + 5CH - 5DH BA + 5EH - 5FH BA + 60H - 61H BA + 62H - 63H BA + 64H - 65H BA + 66H - 67H BA + 68H - 69H BA + 6AH - 6BH BA + 6CH - 6DH BA + 6EH - 6FH BA + 70H - 71H BA + 72H - 73H BA + 74H - 75H BA + 76H - 77H BA + 78H - 79H BA + 7AH - 7BH BA + 7CH - 7DH BA + 7EH - 7FH BA + 80H - BFH BA + C0H - FFH CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR2A CR2B CR2C CR2D CR2E CR2F CR30 CR31 CR32 CR33 CR34 CR35 CR36 CR37 CR38 CR39 CR3A CR3B CR3C CR3D CR3E CR3F CR40-5F CR60-7F Capture Y Frame Buffer 1 Start Address Low Register Capture Y Frame Buffer 1 Start Address High Register Capture U Frame Buffer 0 Start Address Low Register Capture U Frame Buffer 0 Start Address High Register Capture U Frame Buffer 1 Start Address Low Register Capture U Frame Buffer 1 Start Address High Register Capture V Frame Buffer 0 Start Address Low Register Capture V Frame Buffer 0 Start Address High Register Capture V Frame Buffer 1 Start Address Low Register Capture V Frame Buffer 1 Start Address High Register Capture Y Frame Buffer Stride Register Capture UV Frame Buffer Stride Register Video Capture Y FIFO Threshold Register Video Capture UV FIFO Threshold Register Image Maximum Width Register Image Maximum Height Register Compressed Bitstream Buffer 0 Start Address Low Register Compressed Bitstream Buffer 0 Start Address High Register Compressed Bitstream Buffer 1 Start Address Low Register Compressed Bitstream Buffer 1 Start Address High Register Restart Interval Register VLE FIFO Threshold Register Vertical Up-scaling Control Register JPEG Encoder Control Register JPEG Image Size Low Register JPEG Image Size High Register USB FIFO Enable and Threshold Register USB Isochronous Transfer Size Low Register USB Isochronous Transfer Size High Register JPEG/MCTL Test Data Register JPEG Luminance Quantization Table Registers JPEG Chrominance Quantization Table Registers
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8.1 General Control Registers
Miscellaneous Control Register (CR00) Read/Write Power-on Default: 15 FS 14 13 Index: 0000H FF00H 12 11 10 BP 9 8 7 6 5 4 3 R 2 JR 1 UR 0 MR Type MS 24M INTE INTC PWR uC Address: 00H - 01H
SUS ISO RCV PLL
Bit 15
Force Suspend Mode (It reflects status of the MD7 pin upon reset) 0 = Force suspend mode when suspend mode is enabled (CR00_14 = 1) 1 = Normal operation
Bit 14
Suspend Mode Enable (It reflects status of the MD6 pin upon reset) 0 = Disable 1 = Enable
Bit 13
Isochronous Handshake Phase Support (It reflects status of the MD5 pin upon reset) 0 = Enable 1 = Disable
Bit 12
Differential RCV Source (It reflects status of the MD4 pin upon reset) 0 = Generated by the SIE 1 = Generated by the USB transceiver
Bit 11
PLL Enable (It reflects status of the MD3 pin upon reset) 0 = Disable 1 = Enable
Bit 10
High Power Device (It reflects status of the MD2 pin upon reset) 0 = Low power device 1 = High power device
Bit 9
DRAM Type (It reflects status of the MD1 pin upon reset) 0 = EDO DRAM 1 = SDRAM
Bit 8
DRAM Size (It reflects status of the MD0 pin upon reset) 0 = 256Kx DRAM Publication Release Date: March 2000 Revision A1
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1 = 1Mx DRAM Bit 7 CLK24M Output Enable 0 = Disable, CLK24M pin is forced to low 1 = Enable Bit 6 Interrupt Enable 0 = Disable, INT# is forced to inactive high 1 = Enable Bit 5 Interrupt Clear 0 = Normal operation 1 = Clear interrupt, INT# will be cleared to high if enabled. Bit 4 Camera Power-on Control 0 = Power-down 1 = Power-on Note. This register will be cleared to zero when suspended. Bit 3 Bit 2 Reserved JPEG Encoder Reset 0 = Normal operation 1 = Reset JPEG encoder Bit 1 USB FIFO Reset 0 = Normal operation 1 = Reset USB FIFO Bit 0 MD Bus Reset 0 = Normal operation 1 = Reset MD bus (tri-stated)
Serial Bus Control Register (CR01) Read/Write Power-on Default: 15 14 13 Reserved Index: 0001H 0000H 12 11 10 9 8 7 6 5 4 3 2 1 0 EEP MCU XTR Reserved FSB SDE SDR SCR SDW SCW uC Address: 02H - 03H
Bits 15-11 Reserved
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Bit 10 External EEPROM Enable (Read-only, it reflects status of the SDA pin upon reset) 0 = Disable 1 = Enable Bit 9 External Microcontroller Enable (Read-only, it reflects status of the EXTMCU pin) 0 = Disable 1 = Enable Bit 8 USB Transceiver (It reflects status of the INTXTR pin upon reset) 0 = External transceiver 1 = Internal transceiver Bits 7-6 Bit 5 Reserved Fast Serial Bus Write Enable 0 = Disable, serial bus outputs (SDATA and SCLK) are controlled by CR01_1-0 1 = Enable, serial bus outputs (SDATA and SCLK) are controlled by CR06 - CR09. Once CR09 is programmed, all 32-bit data for SDATA and 32-bit data for SCLK from CR06 CR09 will be serially output in 400 Khz bit frequency (2.5 us bit time). Bit 4 Serial Data Enable/Serial Data Strobe 0 = SDE#/SDS pin is driven low 1 = SDE#/SDS pin is driven high Bit 3 Serial Interface Data Read (Read only) 0 = SDATA is low 1 = SDATA is high Bit 2 Serial Interface Clock Read (Read only) 0 = SCLK is low 1 = SCLK is high Bit 1 Serial Interface Data Write 0 = SDATA pin is driven low 1 = SDATA pin is tri-stated Bit 0 Serial Interface Clock Write 0 = SCLK pin is driven low 1 = SCLK pin is tri-state
General I/O Port Control Register (CR02) Read/Write Index: 0002H uC Address: 04H - 05H Publication Release Date: March 2000 Revision A1
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Power-on Default: 15 14 13 0000H 12 11 10 9 8 7 6 5 4 3 2 1 0
P7W P6W P5W P4W P3W P2W P1W P0W P7D P6D P5D P4D P3D P2D P1D P0D
Bits 15-8 GPIO[7:0] Direction 0 = Input 1 = Output Bits 7-0 GPIO[7:0] Data 0 = Low 1 = High Note. GPIO[7:0] pins are used as A[15:8] to the external microcontroller if used (EXTMCU = 1). This register does not control on the GPIO[7:0] pins if an external microcontroller is used.
DRAM Timing Control Register (CR03) Read/Write Power-on Default: 15 R 14 13 Index: 0003H 405DH 12 11 DCT 10 9 8 RAS 7 6 5 4 T_RAS 3 2 RE 1 0 T_RP T_RCD T_CAS uC Address: 06H - 07H
Refresh Cycles
Bit 15
Reserved
Bits 14-12 Refresh Cycles 000 = 1 refresh cycle per horizontal scan line 001 = 2 refresh cycles per horizontal scan line 010 = 3 refresh cycles per horizontal scan line 011 = 4 refresh cycles per horizontal scan line 100 = 5 refresh cycles per horizontal scan line 101 = 6 refresh cycles per horizontal scan line 110 = 7 refresh cycles per horizontal scan line 111 = 8 refresh cycles per horizontal scan line Bit 11 DCT DRAM Data Access 0 = DCT DRAM data access can be interrupted by MCTL when other DRAM request is active. 1 = DCT DRAM data access cannot be interrupted by MCTL.
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Bits 10-9 RAS# Precharge Time Control 00 = 2 MCLKs 01 = 3 MCLKs 10 = 4 MCLKs 11 = 5 MCLKs Bit 8 RAS# Precharge Time Shrink 0 = Not shrink 1 = Shrink by 0.5 MCLK over that specified by bits 10-9 of this register Bits 7-6 RAS# Low to CAS# Low Time Control 00 = 1 MCLK 01 = 2 MCLKs 10 = 3 MCLKs 11 = 4 MCLKs Bits 5-3 Refresh Cycle RAS# Low Pulse Width Control 000 ~ 111 = 1 ~ 8 MCLK cycles Bit 2 RAS# Low Extend 0 = Not extend 1 = Extend 1 MCLK Bits 1-0 CAS# Low Stretch Control 00 = Not stretch 01 = Stretch approximately 1 ns 10 = Stretch approximately 2 ns 11 = Stretch approximately 3 ns
SDRAM Control Register (CR04) Read/Write Power-on Default: 15 14 13 Index: 0004H 0030H 12 11 Reserved 10 9 8 7 6 5 4 3 BTyp 2 1 0 Read Latency Burst Length uC Address: 08H - 09H
Bits 15-7 Reserved Bits 6-4 Read Latency
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000 = Reserved 001 = 1 clock 010 = 2 clocks 011 = 3 clocks 100 ~ 111 = Reserved Bit 3 Burst Type 0 = Sequential 1 = Interleaved Bits 2-0 Burst Length Bits 2-0 000 001 010 011 100 101 110 111 Burst Length Sequential (Bit 3 =0) Interleaved (Bit 3 = 1) 1 1 2 2 4 4 8 8 Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Memory Controller Test Mode Control Register (CR05) Read/Write Power-on Default: 15 14 13 Index: 0005H 0000H 12 11 10 9 8 7 TEN 6 HD 5 SR 4 Test 3 R 2 1 MTS 0 Reserved uC Address: 0AH - 0BH
Bits 15-8 Reserved Bit 7 Memory Controller Test Mode Enable 0 = Disable 1 = Enable Bit 6 DRAM Controller Hold Control 0 = Normal operation 1 = Hold DRAM Controller operation Bit 5 SDRAM Self Refresh 0 = Disable 1 = Enable - 48 -
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Bit 4 Bit 3 Bits 2-0 SDRAM Delay Test (used for test mode only) Reserved Memory Controller Test Mode Select
Fast Serial Bus Write Registers 0~3 (CR06~CR09) Read/Write Power-on Default: CR06 15 C7 CR07 15 CR08 15 CR09 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 10 9 8 7 6 5 4 3 C9 2 D9 1 C8 0 D8 14 D7 13 C6 12 D6 11 C5 10 D5 9 C4 8 D4 7 C3 6 D3 5 C2 4 D2 3 C1 2 D1 1 C0 0 D0 Index: 0006H - 0009H 0000H uC Address: 0CH - 13H
C15 D15 C14 D14
C13 D13 C12 D12 C11 D11 C10 D10
C23 D23 C22 D22
C21 D21 C20 D20 C19 D19 C18 D18
C17 D17 C16 D16
C31 D31 C30 D30
C29 D29 C28 D28 C27 D27 C26 D26
C25 D25 C24 D24
D[31:0] C[31:0]
32-bit data for SDATA output. When fast serial bus is enabled (CR01_5 = 1), D[31:0] will be output serially from LSB to MSB once CR09 is programmed. 32-bit data for SCLK output. When fast serial bus is enabled (CR01_5 = 1), C[31:0] will be output serially from LSB to MSB once CR09 is programmed.
uC Access DRAM Start Address Low Register (CR0C) Read/Write Power-on Default: 15 14 13 Index: 000CH XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 uCA[15:0] uC Address: 18H - 19H
Bits 15-0 uC Access DRAM Start Address Low Publication Release Date: March 2000 Revision A1
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A 21-bit value specifies the WORD offset from the start of the frame buffer for the external microcontroller access. This register contains 16 lower-order bits of the value. Bits 20-16 are located at CR0D_4-0.
uC Access DRAM Start Address High Register (CR0D) Read/Write Power-on Default: 15 14 13 Index: 000DH XXXXH 12 Reserved 11 10 9 8 R/W 7 6 Reserved 5 4 3 2 uCA[20:16] 1 0 uC Address: 1AH - 1BH
Bits 15-9 Reserved Bit 8 uC Access DRAM Mode 0 = Read mode. uC reads data from DRAM. 1 = Write mode. uC writes data to DRAM. Bits 7-5 Bits 4-0 Reserved uCA[20:16]
uC Access DRAM Data Port Register (CR0E) Read/Write Power-on Default: 15 14 13 Index: 000EH XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 Low Byte Data uC Address: 1CH - 1DH
High Byte Data
Bits 15-8 High Byte Data Bits 7-0 Low Byte Data
Vendor String Data Port Register (CR0F) Write-only Power-on Default: 15 14 13 Index: 000FH XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 Vendor String Data Port uC Address: 1EH - 1FH
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Bits 15-0 Vendor String Data Port Maximum 128 bytes IHV-specific information can be provided by the microcontroller through this data port. This data port can be written by the microcontroller only and is prohibted from the USB interface accessing.
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8.2
Video Input Control Registers
Cropping Window Start X Register (CR10) Read/Write Power-on Default: 15 14 13 Reserved Index: 0010H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 Cropping Window Start X uC Address: 20H - 21H
Bits 15-10 Reserved Bits 11-0 Cropping Window Start X A 12-bit value specifies the number of pixels between the inactive edge of HS and the first cropped video pixel.
Cropping Window Start Y Register (CR11) Read/Write Power-on Default: 15 14 13 Reserved Index: 0011H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 Cropping Window Start Y uC Address: 22H - 23H
Bits 15-11 Reserved Bits 10-0 Cropping Window Start Y An 11-bit value specifies the number of lines between the inactive edge of VS and the first cropped video data line.
Cropping Window End X Register (CR12) Read/Write Power-on Default: 15 14 13 Reserved Index: 0012H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 Cropping Window End X uC Address: 24H - 25H
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Bits 15-12 Reserved Bits 10-1 Cropping Window End X A 12-bit value specifies the number of pixels between the inactive edge of HS and the last cropped video pixel.
Cropping Window End Y Register (CR13) Read/Write Power-on Default: 15 14 13 Reserved Index: 0013H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 Cropping Window End Y uC Address: 26H - 27H
Bits 15-11 Reserved Bits 10-0 Cropping Window End Y An 11-bit value specifies the number of lines between the inactive edge of VS and the last cropped video data line.
Captured Video Width Register (CR14) Read/Write Power-on Default: 15 14 13 Reserved Index: 0014H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 Captured Video Width uC Address: 28H - 29H
Bits 15-11 Reserved Bits 10-0 Captured Video Width An 11-bit value specifies the width in pixel of the captured video which is down-scaled (or not) from the cropped video. CR14 CR12 - CR10. Down-scaling is automatically done by an internal DDA (Digital Differential Accumulator).
Captured Video Height Register (CR15) Read/Write Power-on Default: Index: 0015H XXXXH uC Address: 2AH - 2BH
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15 14 13 Reserved 12 11 10 9 8 7 6 5 4 3 2 1 0
Captured Video Height
Bits 15-11 Reserved Bits 10-0 Captured Video Height An 11-bit value specifies the height in line of the captured video which is down-scaled (or not) from the cropped video. CR15 CR13 - CR11. Down-scaling is automatically done by an internal DDA (Digital Differential Accumulator).
Video Capture Control Register (CR16) Read/Write Power-on Default: 15 VCE 14 13 CAPCTL Index: 0016H 0000H 12 11 10 9 8 7 6 5 4 3 2 1 0 VSP HSP VIM VI Format DBE DBS CLM CKF FTE FTM VC Format uC Address: 2CH - 2DH
Bit 15
Video Capture Enable 0 = Disable 1 = Enable
Bits 14-13 Video Capture Control 00 = Capture all received fields/frames video data 01 = Capture every other received fields/frames video data 10 = Capture and hold after one frame/field (non-interlaced/interlaced mode) 11 = Reserved Bit 12 VS Input Pin Polarity 0 = Negative sync pulse 1 = Positive sync pulse Bit 11 HS Input Pin Polarity 0 = Negative sync pulse 1 = Positive sync pulse Bit 10 Input Video Mode 0 = 16-bit mode 1 = 8-bit mode Bits 9-8 Input Video Data Format - 54 -
W99681CF
YUV Input Video Data Format 8-bit Mode (Y[7:0]) 16-bit Mode (UV[7:0]) Y, U, Y, V, ... U, V, U, V, ... U, Y, V, Y, ... U, V, U, V, ... Y, V, Y, U, ... V, U, V, U, ... V, Y, U, Y, ... V, U, V, U, ...
Bits 9-8 00 01 10 11 Bit 7 Double Buffering Enable 0 = Disable 1 = Enable Bit 6
Double Buffering Status (Read-only) 0 = Buffer 0 active 1 = Buffer 1 active
Bit 5
Video Data Clamping Enable (Clamped to CCIR-601 Format) 0 = Disable 1 = Enable (Y is clamped to 16 - 235, UV is clamped to 16 - 240)
Bit 4
VICLK Falling Edge Latch 0 = Input video data and signals are latched by rising edge of VICLK 1 = Input video data and signals are latched by falling edge of VICLK
Bit 3
Filter Enable 0 = Disable 1 = Enable
Bit 2
Filter Type 0 = 1-2-1 filter 1 = 2-3-6-3-2 filter
Bits 1-0
Captured Video Data Format 00 = YUV4:2:2 packed mode 01 = YUV4:2:0 packed mode 10 = YUV4:2:2 planar mode 11 = YUV4:2:0 planar mode
Video Capture Test Mode Control Register (CR17) Read/Write Power-on Default: Index: 0017H 0000H uC Address: 2EH - 2FH
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15 14 13 12 11 10 9 8 7 TEN 6 5 4 3 2 1 0
Reserved
Reserved
Video Test Selection
Bits 15-8 Reserved Bit 7 Video Capture Test Mode Enable 0 = Normal operation 1 = Test mode enable Bits 6-5 Bits 4-0 Reserved Video Capture Test Mode Selection
Capture Test Data Register (CR18) Read/Write Power-on Default: 15 14 13 Index: 0018H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 Capture Test Data uC Address: 30H - 31H
Bits 15-0 Capture Test Data (used for test mode only)
Capture Y Frame Buffer 0 Start Address Low Register (CR20) Read/Write Power-on Default: 15 14 13 Index: 0020H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPYSA0[15:0] uC Address: 40H - 41H
Bits 15-0 Capture Y Frame Buffer 0 Start Address Low A 21-bit value specifies the WORD offset from the start of the frame buffer for buffer 0 (packed mode), or Y components (planar mode) of the captured video. Buffer 0 is always used, no matter double buffering is enabled or disabled. This register contains 16 lowerorder bits of the value. Bits 20-16 are located at CR17_4-0.
Capture Y Frame Buffer 0 Start Address High Register (CR21)
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Read/Write Power-on Default: 15 14 13 Index: 0021H XXXXH 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 CAPYSA0[20:16] uC Address: 42H - 43H
Bits 15-5 Reserved Bits 4-0 CAPYSA0[20:16]
Capture Y Frame Buffer 1 Start Address Low Register (CR22) Read/Write Power-on Default: 15 14 13 Index: 0022H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPYSA1[15:0] uC Address: 44H - 45H
Bits 15-0 Capture Y Frame Buffer 1 Start Address Low A 21-bit value specifies the WORD offset from the start of the frame buffer for buffer 1 (packed mode), or Y components (planar mode) of the captured video. Buffer 1 is not used if double buffering is disabled. This register contains 16 lower-order bits of the value. Bits 20-16 are located at CR19_4-0.
Capture Y Frame Buffer 1 Start Address High Register (CR23) Read/Write Power-on Default: 15 14 13 Index: 0023H XXXXH 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 CAPYSA1[20:16] uC Address: 46H - 47H
Bits 15-5 Reserved Bits 4-0 CAPYSA1[20:16]
Capture U Frame Buffer 0 Start Address Low Register (CR24) Read/Write Index: 0024H uC Address: 48H - 49H
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Power-on Default: 15 14 13 XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPUSA0[15:0]
Bits 15-0 Capture U Frame Buffer 0 Start Address Low A 21-bit value specifies the WORD offset from the start of the frame buffer for U components (planar mode) of the captured video. It is not used if the captured video is in packed mode. Buffer 0 is always used, no matter double buffering is enabled or disabled. This register contains 16 lower-order bits of the value. Bits 20-16 are located at CR1B_4-0.
Capture U Frame Buffer 0 Start Address High Register (CR25) Read/Write Power-on Default: 15 14 13 Index: 0025H XXXXH 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 CAPUSA0[20:16] uC Address: 4AH - 4BH
Bits 15-5 Reserved Bits 4-0 CAPUSA0[20:16]
Capture U Frame Buffer 1 Start Address Low Register (CR26) Read/Write Power-on Default: 15 14 13 Index: 0026H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPUSA1[15:0] uC Address: 4CH - 4DH
Bits 15-0 Capture U Frame Buffer 1 Start Address Low A 21-bit value specifies the WORD offset from the start of the frame buffer for U components (planar mode) of the captured video. It is not used if the captured video is in packed mode. Buffer 1 is not used if double buffering is disabled. This register contains 16 lower-order bits of the value. Bits 20-16 are located at CR1D_4-0.
Capture U Frame Buffer 1 Start Address High Register (CR27) Read/Write Index: 0027H uC Address: 4EH - 4FH - 58 -
W99681CF
Power-on Default: 15 14 13 XXXXH 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 CAPUSA1[20:16]
Bits 15-5 Reserved Bits 4-0 CAPUSA1[20:16]
Capture V Frame Buffer 0 Start Address Low Register (CR28) Read/Write Power-on Default: 15 14 13 Index: 0028H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPVSA0[15:0] uC Address: 50H - 51H
Bits 15-0 Capture V Frame Buffer 0 Start Address Low A 21-bit value specifies the WORD offset from the start of the frame buffer for V components (planar mode) of the captured video. It is not used if the captured video is in packed mode. Buffer 0 is always used, no matter double buffering is enabled or disabled. This register contains 16 lower-order bits of the value. Bits 20-16 are located at CR1F_4-0.
Capture V Frame Buffer 0 Start Address High Register (CR29) Read/Write Power-on Default: 15 14 13 Index: 0029H XXXXH 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 CAPVSA0[20:16] uC Address: 52H - 53H
Bits 15-5 Reserved Bits 4-0 CAPVSA0[20:16]
Capture V Frame Buffer 1 Start Address Low Register (CR2A) Read/Write Power-on Default: Index: 002AH XXXXH uC Address: 54H - 55H
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPVSA1[15:0]
Bits 15-0 Capture V Frame Buffer 1 Start Address Low A 21-bit value specifies the WORD offset from the start of the frame buffer for V components (planar mode) of the captured video. It is not used if the captured video is in packed mode. Buffer 1 is not used if double buffering is disabled. This register contains 16 lower-order bits of the value. Bits 20-16 are located at CR21_4-0.
Capture V Frame Buffer 1 Start Address High Register (CR2B) Read/Write Power-on Default: 15 14 13 Index: 002BH XXXXH 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 CAPVSA1[20:16] uC Address: 56H - 57H
Bits 15-5 Reserved Bits 4-0 CAPVSA1[20:16]
Capture Y Frame Buffer Stride Register (CR2C) Read/Write Power-on Default: 15 14 13 Reserved Index: 002CH XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPYS[10:0] uC Address: 58H - 59H
Bits 15-11 Reserved Bits 10-0 Capture Y Frame Buffer Stride This register specifies the WORD offset of vertically adjacent pixels (packed mode), or vertically adjacent Y components of the captured video. It is used for both buffer 0 and buffer 1.
Capture UV Frame Buffer Stride Register (CR2D) Read/Write Index: 002DH uC Address: 5AH - 5BH
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Power-on Default: 15 14 13 XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPYS[9:0]
Reserved
Bits 15-10 Reserved Bits 9-0 Capture UV Frame Buffer Stride This register specifies the WORD offset of vertically adjacent U or V components of the captured video which is in planar mode. It is used for both buffer 0 and buffer 1. It is not used if the captured video is in packed mode.
Video Capture Y FIFO Threshold Register (CR2E) Read/Write Power-on Default: 15 14 Reserved 13 Index: 002EH 0804H 12 11 10 9 8 7 6 Reserved 5 4 3 2 1 0 VCAPY_HT[4:0] VCAPY_LT[4:0] uC Address: 5CH - 5DH
Bits 15-13 Reserved Bits 12-8 Video Capture Y FIFO High Threshold When video capture FIFO (packed mode), or Y FIFO (planar mode) is filled to this threshold, a request is generated to the DRAM controller for DRAM access. Initial value is 08H. Bits 7-5 Bits 4-0 Reserved Video Capture Y FIFO Low Threshold When video capture FIFO (packed mode), or Y FIFO (planar mode) is fetched to this threshold by DRAM controller, the FIFO is ready to release DRAM access to other pending requests. Initial value is 04H.
Video Capture UV FIFO Threshold Register (CR2F) Read/Write Power-on Default: 15 14 13 VCAPU_HT[3:0] Index: 002FH 8484H 12 11 10 9 8 7 6 5 4 3 2 1 0 VCAPU_LT[3:0] VCAPV_HT[3:0] VCAPV_LT[3:0] uC Address: 5EH - 5FH
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Bits 15-12 Video Capture U FIFO High Threshold When video capture U FIFO (planar mode) is filled to this threshold, a request is generated to the DRAM controller for DRAM access. It is not used if the captured video is in packed mode. Initial value is 08H. Bits 11-8 Video Capture U FIFO Low Threshold When video capture U FIFO (planar mode) is fetched to this threshold by DRAM controller, the FIFO is ready to release DRAM access to other pending requests. It is not used if the captured video is in packed mode. Initial value is 04H. Bits 7-4 Video Capture V FIFO High Threshold When video capture V FIFO (planar mode) is filled to this threshold, a request is generated to the DRAM controller for DRAM access. It is not used if the captured video is in packed mode. Initial value is 08H. Bits 3-0 Video Capture V FIFO Low Threshold When video capture V FIFO (planar mode) is fetched to this threshold by DRAM controller, the FIFO is ready to release DRAM access to other pending requests. It is not used if the captured video is in packed mode. Initial value is 04H.
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8.3 JPEG Encoder Control Registers
Image Maximum Width Register (CR30) Read/Write Power-on Default: 15 14 13 Reserved Index: 0030H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 MAXW[10:0] uC Address: 60H - 61H
Bits 15-11 Reserved Bits 10-0 Image Maximum Width
Image Maximum Height Register (CR31) Read/Write Power-on Default: 15 14 13 Reserved Index: 0031H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 MAXH[10:0] uC Address: 62H - 63H
Bits 15-11 Reserved Bits 10-0 Image Maximum Height
Compressed Bitstream Buffer 0 Start Address Low Register (CR32) Read/Write Power-on Default: 15 14 13 Index: 0032H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 BSSA0[15:0] uC Address: 64H - 65H
Bits 15-0 Compressed Bitstream Buffer 0 Start Address Low A 21-bit value specifies the WORD offset from the start of the frame buffer for the compressed bitstream buffer 0. Bits 20-16 are located at CR33_4-0. Publication Release Date: March 2000 Revision A1
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Compressed Bitstream Buffer 0 Start Address High Register (CR33) Read/Write Power-on Default: 15 14 13 Index: 0033H XXXXH 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 BSSA0[20:16] uC Address: 66H - 67H
Bits 15-5 Reserved Bits 4-0 BSSA0[20:16]
Compressed Bitstream Buffer 1 Start Address Low Register (CR34) Read/Write Power-on Default: 15 14 13 Index: 0034H XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 BSSA1[15:0] uC Address: 68H - 69H
Bits 15-0 Compressed Bitstream Buffer 1 Start Address Low A 21-bit value specifies the WORD offset from the start of the frame buffer for the compressed bitstream buffer 1. Bits 20-16 are located at CR35_4-0.
Compressed Bitstream Buffer 1 Start Address High Register (CR35) Read/Write Power-on Default: 15 14 13 Index: 0035H XXXXH 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 BSSA1[20:16] uC Address: 6AH - 6BH
Bits 15-5 Reserved Bits 4-0 BSSA1[20:16]
Restart Interval Register (CR36) Read/Write Index: 0036H uC Address: 6CH - 6DH
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Power-on Default: 15 14 13 0000H 12 11 10 9 8 7 6 5 4 3 2 1 0 Restart Interval
Bits 15-0 Restart Interval Specifies the number of MCU (Minimum Coded Unit) in the restart interval. Restart interval processing is disabled if this value is 0.
VLE FIFO Threshold Register (CR37) Read/Write Power-on Default: 15 14 13 Reserved Index: 0037H 0804H 12 11 10 9 8 7 6 5 4 3 2 1 0 VLE_HT[3:0] Reserved VLE_LT[3:0] uC Address: 6EH - 6FH
Bits 15-12 Reserved Bits 11-8 VLE FIFO High Threshold When VLE FIFO is filled with JPEG coded bitstream to this threshold, a request is generated to the DRAM controller for DRAM access. Initial value is 08H. Bits 7-4 Bits 3-0 Reserved VLE FIFO Low Threshold When VLE FIFO is fetched to this threshold by DRAM controller, the FIFO is ready to release DRAM access to other pending requests. Initial value is 04H.
Vertical Up-scaling Control Register (CR38) Read/Write Power-on Default: 15 EN 14 13 Index: 0038H 0000H 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 Vertical Up-scaling Factor uC Address: 70H - 71H
Bit 15
Vertical Up-scaling Enable 0 = Disable 1 = Enable Publication Release Date: March 2000 Revision A1
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Bits 14-6 Reserved Bits 5-0 Vertical Up-scaling Factor Up-scaling ratio (Scaled Height/Original Height) = 1.x, where x = Vertical Up-scaling Factor/64. The maximum 2x up-scaling will be done if 0 is programmed.
JPEG Encoder Control Register (CR39) Read/Write Power-on Default: 15 14 13 Index: 0039H 0000H 12 Reserved 11 10 9 8 QRD 7 6 Reserved 5 4 3 2 1 0 R JCLK Test TEN JEN uC Address: 72H - 73H
Bits 15-9 Reserved Bit 8 JPEG Quantization Table Registers (CR40 ~ CR7F) Read Enable 0 = Disable 1 = Enable Bits 7-5 Bit 4 Reserved JPEG Clock Enable (Must be enabled before JPEG Q-table access or encoding) 0 = Disable 1 = Enable Bit 3 Bit 2 JPEG Test (used for test mode only) JPEG Test Mode Enable 0 = Disable 1 = Enable Bit 1 JPEG Encoder Enable 0 = Disable 1 = Enable Bit 0 Reserved
JPEG Image Size Low Register (CR3A) Read-only Power-on Default: 15 14 13 Index: 003AH XXXXH 12 11 10 9 8 7 - 66 6 5 4 3 2 1 0 uC Address: 74H - 75H
W99681CF
JIMG_SIZE[15:0]
Bits 15-0 JPEG Image Size Low A 21-bit value specifies the JPEG compressed image size in WORD. It is used by the microcontroller to determine starting address for the next still image. This register contains the 16 lower-order bits of the value. Bits 20-16 are located at CR3B_4-0.
JPEG Image Size High Register (CR3B) Read-only Power-on Default: 15 14 13 Index: 003BH XXXXH 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 JIMG_SIZE _SIZE[20:16] uC Address: 76H - 77H
Bits 15-5 Reserved Bits 4-0 JPEG Image Size High This register contains the 4 high-order bits of the JPEG Image Size.
USB FIFO Enable and Threshold Register (CR3C) Read/Write Power-on Default: 15 UEN 14 13 Reserved Index: 003CH 0A05H 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_HT[3:0] Reserved USB_LT[3:0] uC Address: 78H - 79H
Bit 15
USB Isochronous Pipe Transfer Enable 0 = Disable 1 = Enable
Bits 14-12 Reserved Bits 11-8 USB FIFO High Threshold Bits 7-4 Bits 3-0 Reserved USB FIFO Low Threshold
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USB Isochronous Transfer Size Low Register (CR3D) Read/Write Power-on Default: 15 14 13 Index: 003DH XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 ISO_SIZE[15:0] uC Address: 7AH - 7BH
Bits 15-0 USB Isochronous Transfer Size Low A 21-bit value specifies the USB Isochronous Transfer Size in WORD for the original video transfer or the still image transfer. It is not used for the JPEG compression video transfer mode (CR39_1 = 1). This register contains the 16 lower-order bits of the value. Bits 20-16 are located at CR3E_4-0.
USB Isochronous Transfer Size High Register (CR3E) Read/Write Power-on Default: 15 14 13 Index: 003EH XXXXH 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 ISO_SIZE[20:16] uC Address: 7CH - 7DH
Bits 15-5 Reserved Bits 4-0 USB Isochronous Transfer Size High This register contains the 4 high-order bits of the USB Isochronous Transfer Size. It is not used for the JPEG compression video transfer mode (CR39_1 = 1).
JPEG/MCTL Test Data Register (CR3F) Read/Write Power-on Default: 15 14 13 Index: 003FH XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 JPEG/MCTL Test Data uC Address: 7EH - 7FH
Bits 15-0 JPEG/MCTL Test Data (used for test mode only)
JPEG Luminance Quantization Table Registers (CR40 -- CR5F)
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Read/Write Power-on Default: 15 14 13 Index: 0040H - 005FH XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 JPEG Luminance Quantization Table uC Address: 80H - BFH
Bits 15-0 JPEG Luminance Quantization Table Note. These registers can be read only when CR39 bit 8 is enabled (CR39_8 = 1).
JPEG Chrominance Quantization Table Registers (CR60 -- CR7F) Read/Write Power-on Default: 15 14 13 Index: 0060H - 007FH XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 JPEG Chrominance Quantization Table uC Address: C0H - FFH
Bits 15-0 JPEG Chrominance Quantization Table Note. These registers can be read only when CR39 bit 8 is enabled (CR39_8 = 1).
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9
ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
Table 9.1 Absolute Maximum Ratings Ambient temperature Storage temperature DC supply voltage I/O pin voltage with respect to VSS 0 C to 70 C -40 C to 125 C -0.5V to 7V -0.5V to VDD + 0.5V
9.2
DC Characteristics
9.2.1 USB Transceiver DC Characteristics Table 9.2 USB Transceiver DC Characteristics Symbol VDI VCM VSE VOL VOH VCRS ZDRV CIN Parameter Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Static Output Low Voltage Static Output High Voltage Output Signal Crossover Voltage Driver Output Resistance Pin Capacitance Steady state drive RL of 1.5 K to 3.6 V RL of 15 K to VSS 2.8 1.3 28 Conditions DP - DM Includes VDI range Min. 0.2 0.8 0.8 2.5 2.0 0.3 3.6 2.0 43 20 Max. Unit V V V V V V pF
9.2.2 Digital DC Characteristics Table 9.3 Digital DC Characteristics Symbol VDD5V VDD VIL VIH VOL VOH Parameter 5V Power Supply 3.3V Power Supply Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage - 70 2.4 Conditions Min. 4.40 3.0 -0.5 2.0 VSS+0.4 Max. 5.25 3.6 0.8 Unit V V V V V V
W99681CF
IIL IIH IUP CIO IPD IDD Input Low Leakage Current Input High Leakage Current Pull-up Current Pin Capacitance Powerdown Current USB Suspend Active Current FCLK = 12 MHz VIN = 0.4V VIN = 2.4V VIN = 0V -133.2 +70 -70 -400.6 10 200 120 A A A pF A mA
9.3 AC Characteristics
9.3.1 USB Transceiver AC Characteristics
Rise Time CL Differential Data Lines 10% CL Full Speed: 4 to 20ns at CL = 50pF 90% 90%
Fall Time
10%
tR
tF
Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF
Figure 9.1 Data Signal Rise and Fall Time
TPERIOD Differential Data Lines
Crossover Points
Consecutive Transitions N * TPERIOD + TxJR1 Paired Transitions N * TPERIOD + TxJR2
Figure 9.2 Differential Data Jitter
TPERIOD Differential Data Lines
Crossover Point
Crossover Point Extended
Diff. Data to SE0 Skew N * TPERIOD + TDEOP
Source EOP Width:
TEOPT
Receiver EOP Width: TEOPR1, TEOPR2
Figure 9.3 Differential to EOP Transition Skew and EOP Width
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TPERIOD Differential Data Lines
T JR T JR1 T JR2
Consecutive Transitions N * TPERIOD + TJR1 Paired Transitions N * TPERIOD + TJR2
Figure 9.4 Receiver Jitter Tolerance Table 9.4 USB Transceiver AC Characteristics Symbol TR TF TRFM TDRATE Parameter Rise Time Fall Time Rise/Fall Time Matching Full Speed Data Rate Average bit rate (12 Mb/s 0.25%) Source Differential Driver Jitter TDJ1 TDJ2 TEOPT TDEOP TJR1 TJR2 TEOPR1 TEOPR2 To Next Transition For Paired Transitions Source EOP Width Differential to EOP Transition Skew Receiver Data Jitter Tolerance To Next Transition For Paired Transitions EOP Width at Receiver Must Reject as EOP Must Accept as EOP 40 82 ns ns -18.5 -9 18.5 9 ns ns -3.5 -4.0 160 -2 3.5 4.0 175 5 ns ns ns ns Conditions CL = 50 pF CL = 50 pF Min. 4 4 90 11.97 Max. 20 20 110 12.03 Unit ns ns % Mbps
9.3.2 RESET Timing AC Characteristics
RSTIN#
TRST
Figure 9.5 RESET Timing - 72 -
W99681CF
Table 9.5 RESET Timing Symbol TRST Parameter Reset Pulse Width Conditions Min. 100 Max. Unit ns
9.3.3 Clock AC Characteristics
TCYC THIGH TLOW
2.0 V 1.5 V 0.8 V
Figure 9.6 Clock Waveform Table 9.6 Clock AC Characteristics Symbol 1/TCYC Parameter Oscillator Frequency VICLK Frequency SMCLK Frequency THIGH Oscillator Clock High Time VICLK Clock High Time SMCLK Clock High Time TLOW Oscillator Clock Low Time VICLK Clock Low Time SMCLK Clock Low Time 9.3.4 Input Video AC Characteristics Conditions Min. 11.988 5 47.88 33 5 8.3 33 5 8.3 12.5 12.5 50 Max. 12.012 30 48.12 50 Unit MHz MHz MHz ns ns ns ns ns ns
VICLK TSU Y[7:0], UV[7:0] HS, VS
1.5 V
1.5 V
TH
1.5 V
input valid
Figure 9.7 Input Video Timing Publication Release Date: March 2000 Revision A1
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Table 9.7 Input Video AC Characteristics Symbol TSU TH Parameter Y[7:0], UV[7:0], HS, VS Setup Time Y[7:0], UV[7:0], HS, VS Hold Time Conditions Min. 6 4 Max. Unit ns ns
9.3.5 DRAM Interface AC Characteristics
SMCLK TSU MD[15:0]
1.5 V
1.5 V
TH
1.5 V
input valid
Figure 9.8 DRAM Interface Input Timing
SMCLK
1.5 V
TVAL OUTPUT DELAY
1.5 V
Figure 9.9 DRAM Interface Output Timing Table 9.8 DRAM Interface AC Characteristics Symbol TSU TH TH Parameter MD[15:0] Setup Time MD[15:0] Hold Time MD[15:0], MA[10:0], BA, RAS[1:0]#/CS[1:0]#, CAS[1:0]#/DQM[1:0], OE#/CKE, WE#, SRAS#, SCAS# Conditions Min. 0 7 2 7 Max. Unit ns ns ns
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9.3.6 EEPROM Interface AC Characteristics
THIGH
TLOW SCL TSU.STA SDA IN TAA SDA OUT THD.STA
THD.DAT
TSU.DAT
TSU.STO
TDH
TBUF
Figure 9.10 EEPROM Interface Timing Table 9.9 EEPROM Interface AC Characteristics Symbol FSCL TLOW THIGH TAA TBUF THD.STA TSU.STA THD.DAT TSU.DAT TR TF TSU.STO TDH Parameter SCL Clock Frequency Clock Pulse Width Low Clock Pulse Width High Clock Low to Data Out Valid Time the bus must be free before a new transmission can start Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time Inputs Fall Time Stop Set-up Time Data Out Hold Time 4.7 100 4.7 4.0 0.1 4.7 4.0 4.7 0 200 1.0 300 4.5 Conditions Min. Max. 100 Unit KHz s s s s s s s ns s ns s ns
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9.3.7 Microcontroller Interface AC Characteristics
ALE A[15:8]
TAS TAH
AD[7:0]
A[7:0] TDAR TDDA
D[7:0] TRDH
RD#
TRD
AD[7:0]
A[7:0]
D[7:0] TWR TWDH
WR#
TDAW
Figure 9.11 Microcontroller Interface Timing Table 9.10 Microcontroller Interface AC Characteristics Symbol TAS TAH TDAR TDDA TRDH TRD TDAW TWDH TWR Parameter Address Set-up Time Address Hold Time ALE Low to RD# Low RD# Low to Data Valid Read Data Hold Time RD# Pulse Width ALE Low to WR# Low Write Data Hold Time WR# Pulse Width 3 2 TMCLK 10 5 2 TMCLK Conditions Min. 5 5 10 TMCLK + 5 Max. Unit ns ns ns ns ns ns ns ns ns
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10
PACKAGE SPEC.
HD D 128 1 103 102
E HE
38 39 b 64
65
e
c A
A2
See Detail F Seating Plane A1 y L L1 Detail F
Symbol
Dimension in inch
Dimension in mm
Min
0.004 0.101 0.006 0.004 0.547 0.783
Nom
Max
0.134
Min
0.10
Nom
Max
3.40
A A1 A2 b c D E e HD HE L L1 y 0
0.107 0.008 0.006 0.551 0.787 0.020
0.113 0.010 0.010 0.555 0.791
2.57 0.15 0.10 13.90 19.90
2.72 0.20 0.15 14.00 20.00 0.50
2.87 0.25 0.25 14.10 20.10
0.669 0.905 0.023 0.055
0.677 0.913 0.031 0.063
0.685 0.921 0.039 0.071 0.004
17.00 23.00 0.60 1.40
17.20 23.20 0.80 1.60
17.40 23.40 1.00 1.80 0.10
0
12
0
12
Figure 10.1 128L QFP (14x20x2.75mm footprint 3.2mm) Dimensions
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11
ORDERING INFORMATION
Package 128L QFP
Part Number W99681CF
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
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